Statistics
| Branch: | Tag: | Revision:

amiro-os / modules / NUCLEO-L476RG / mcuconf.h @ 3cb82b1a

History | View | Annotate | Download (14.5 KB)

1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

    
19
#ifndef MCUCONF_H
20
#define MCUCONF_H
21

    
22
/*
23
 * STM32L1xx drivers configuration.
24
 * The following settings override the default settings present in
25
 * the various device driver implementation headers.
26
 * Note that the settings for each driver only have effect if the whole
27
 * driver is enabled in halconf.h.
28
 *
29
 * IRQ priorities:
30
 * 15...0       Lowest...Highest.
31
 *
32
 * DMA priorities:
33
 * 0...3        Lowest...Highest.
34
 */
35

    
36
#define STM32L4xx_MCUCONF
37

    
38
/*
39
 * HAL driver system settings.
40
 */
41
#define STM32_NO_INIT                       FALSE
42
#define STM32_VOS                           STM32_VOS_RANGE1
43
#define STM32_PVD_ENABLE                    FALSE
44
#define STM32_PLS                           STM32_PLS_LEV0
45
#define STM32_HSI16_ENABLED                 FALSE
46
#define STM32_LSI_ENABLED                   TRUE
47
#define STM32_HSE_ENABLED                   FALSE
48
#define STM32_LSE_ENABLED                   TRUE
49
#define STM32_MSIPLL_ENABLED                TRUE
50
#define STM32_ADC_CLOCK_ENABLED             TRUE
51
#define STM32_USB_CLOCK_ENABLED             TRUE
52
#define STM32_SAI1_CLOCK_ENABLED            TRUE
53
#define STM32_SAI2_CLOCK_ENABLED            TRUE
54
#define STM32_MSIRANGE                      STM32_MSIRANGE_4M
55
#define STM32_MSISRANGE                     STM32_MSISRANGE_4M
56
#define STM32_SW                            STM32_SW_PLL
57
#define STM32_PLLSRC                        STM32_PLLSRC_MSI
58
#define STM32_PLLM_VALUE                    1
59
#define STM32_PLLN_VALUE                    80
60
#define STM32_PLLP_VALUE                    7
61
#define STM32_PLLQ_VALUE                    6
62
#define STM32_PLLR_VALUE                    4
63
#define STM32_HPRE                          STM32_HPRE_DIV1
64
#define STM32_PPRE1                         STM32_PPRE1_DIV1
65
#define STM32_PPRE2                         STM32_PPRE2_DIV1
66
#define STM32_STOPWUCK                      STM32_STOPWUCK_MSI
67
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
68
#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
69
#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
70
#define STM32_PLLSAI1N_VALUE                72
71
#define STM32_PLLSAI1P_VALUE                7
72
#define STM32_PLLSAI1Q_VALUE                6
73
#define STM32_PLLSAI1R_VALUE                6
74
#define STM32_PLLSAI2N_VALUE                72
75
#define STM32_PLLSAI2P_VALUE                7
76
#define STM32_PLLSAI2R_VALUE                6
77
#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
78
#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
79
#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
80
#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK
81
#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK
82
#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
83
#define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK
84
#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK
85
#define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK
86
#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
87
#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1
88
#define STM32_SAI1SEL                       STM32_SAI1SEL_OFF
89
#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF
90
#define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
91
#define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
92
#define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
93
#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
94
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
95

    
96
/*
97
 * IRQ system settings.
98
 */
99
#define STM32_IRQ_EXTI0_PRIORITY            6
100
#define STM32_IRQ_EXTI1_PRIORITY            6
101
#define STM32_IRQ_EXTI2_PRIORITY            6
102
#define STM32_IRQ_EXTI3_PRIORITY            6
103
#define STM32_IRQ_EXTI4_PRIORITY            6
104
#define STM32_IRQ_EXTI5_9_PRIORITY          6
105
#define STM32_IRQ_EXTI10_15_PRIORITY        6
106
#define STM32_IRQ_EXTI1635_38_PRIORITY      6
107
#define STM32_IRQ_EXTI18_PRIORITY           6
108
#define STM32_IRQ_EXTI19_PRIORITY           6
109
#define STM32_IRQ_EXTI20_PRIORITY           6
110
#define STM32_IRQ_EXTI21_22_PRIORITY        15
111

    
112
/*
113
 * ADC driver system settings.
114
 */
115
#define STM32_ADC_DUAL_MODE                 FALSE
116
#define STM32_ADC_COMPACT_SAMPLES           FALSE
117
#define STM32_ADC_USE_ADC1                  FALSE
118
#define STM32_ADC_USE_ADC2                  FALSE
119
#define STM32_ADC_USE_ADC3                  TRUE // turned on
120
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
121
#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 2)
122
#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(1, 3)
123
#define STM32_ADC_ADC1_DMA_PRIORITY         2
124
#define STM32_ADC_ADC2_DMA_PRIORITY         2
125
#define STM32_ADC_ADC3_DMA_PRIORITY         2
126
#define STM32_ADC_ADC12_IRQ_PRIORITY        5
127
#define STM32_ADC_ADC3_IRQ_PRIORITY         5
128
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
129
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
130
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5
131
#define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_AHB_DIV1
132

    
133
/*
134
 * CAN driver system settings.
135
 */
136
#define STM32_CAN_USE_CAN1                  TRUE
137
#define STM32_CAN_CAN1_IRQ_PRIORITY         11
138

    
139
/*
140
 * DAC driver system settings.
141
 */
142
#define STM32_DAC_DUAL_MODE                 FALSE
143
#define STM32_DAC_USE_DAC1_CH1              FALSE
144
#define STM32_DAC_USE_DAC1_CH2              FALSE
145
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
146
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
147
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
148
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
149
#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(2, 4)
150
#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)
151

    
152
/*
153
 * GPT driver system settings.
154
 */
155
#define STM32_GPT_USE_TIM1                  FALSE
156
#define STM32_GPT_USE_TIM2                  FALSE
157
#define STM32_GPT_USE_TIM3                  FALSE
158
#define STM32_GPT_USE_TIM4                  FALSE
159
#define STM32_GPT_USE_TIM5                  FALSE
160
#define STM32_GPT_USE_TIM6                  FALSE
161
#define STM32_GPT_USE_TIM7                  FALSE
162
#define STM32_GPT_USE_TIM8                  FALSE
163
#define STM32_GPT_USE_TIM15                 FALSE
164
#define STM32_GPT_USE_TIM16                 FALSE
165
#define STM32_GPT_USE_TIM17                 FALSE
166
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
167
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
168
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
169
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
170
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
171
#define STM32_GPT_TIM6_IRQ_PRIORITY         7
172
#define STM32_GPT_TIM7_IRQ_PRIORITY         7
173
#define STM32_GPT_TIM8_IRQ_PRIORITY         7
174
#define STM32_GPT_TIM15_IRQ_PRIORITY        7
175
#define STM32_GPT_TIM16_IRQ_PRIORITY        7
176
#define STM32_GPT_TIM17_IRQ_PRIORITY        7
177

    
178
/*
179
 * I2C driver system settings.
180
 */
181
#define STM32_I2C_USE_I2C1                  FALSE
182
#define STM32_I2C_USE_I2C2                  FALSE
183
#define STM32_I2C_USE_I2C3                  TRUE
184
#define STM32_I2C_BUSY_TIMEOUT              50
185
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
186
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
187
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
188
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
189
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
190
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
191
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
192
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
193
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
194
#define STM32_I2C_I2C1_DMA_PRIORITY         3
195
#define STM32_I2C_I2C2_DMA_PRIORITY         3
196
#define STM32_I2C_I2C3_DMA_PRIORITY         3
197
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
198

    
199
/*
200
 * ICU driver system settings.
201
 */
202
#define STM32_ICU_USE_TIM1                  FALSE
203
#define STM32_ICU_USE_TIM2                  FALSE
204
#define STM32_ICU_USE_TIM3                  FALSE
205
#define STM32_ICU_USE_TIM4                  FALSE
206
#define STM32_ICU_USE_TIM5                  FALSE
207
#define STM32_ICU_USE_TIM8                  FALSE
208
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
209
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
210
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
211
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
212
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
213
#define STM32_ICU_TIM8_IRQ_PRIORITY         7
214

    
215
/*
216
 * PWM driver system settings.
217
 */
218
#define STM32_PWM_USE_ADVANCED              FALSE
219
#define STM32_PWM_USE_TIM1                  FALSE
220
#define STM32_PWM_USE_TIM2                  FALSE
221
#define STM32_PWM_USE_TIM3                  FALSE
222
#define STM32_PWM_USE_TIM4                  FALSE
223
#define STM32_PWM_USE_TIM5                  FALSE
224
#define STM32_PWM_USE_TIM8                  FALSE
225
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
226
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
227
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
228
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
229
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
230
#define STM32_PWM_TIM8_IRQ_PRIORITY         7
231

    
232
/*
233
 * QSPI driver system settings.
234
 */
235
#define STM32_QSPI_USE_QUADSPI1             FALSE
236
#define STM32_QSPI_QUADSPI1_DMA_STREAM      STM32_DMA_STREAM_ID(2, 7)
237

    
238
/*
239
 * SDC driver system settings.
240
 */
241
#define STM32_SDC_USE_SDMMC1                FALSE
242
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE
243
#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000
244
#define STM32_SDC_SDMMC_READ_TIMEOUT        1000
245
#define STM32_SDC_SDMMC_CLOCK_DELAY         10
246
#define STM32_SDC_SDMMC1_DMA_PRIORITY       3
247
#define STM32_SDC_SDMMC1_IRQ_PRIORITY       9
248
#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID(2, 4)
249

    
250
/*
251
 * SERIAL driver system settings.
252
 */
253
#define STM32_SERIAL_USE_USART1             FALSE
254
#define STM32_SERIAL_USE_USART2             TRUE
255
#define STM32_SERIAL_USE_USART3             FALSE
256
#define STM32_SERIAL_USE_LPUART1            FALSE
257
#define STM32_SERIAL_USART1_PRIORITY        12
258
#define STM32_SERIAL_USART2_PRIORITY        12
259
#define STM32_SERIAL_USART3_PRIORITY        12
260
#define STM32_SERIAL_LPUART1_PRIORITY       12
261

    
262
/*
263
 * SPI driver system settings.
264
 */
265
#define STM32_SPI_USE_SPI1                  FALSE
266
#define STM32_SPI_USE_SPI2                  FALSE
267
#define STM32_SPI_USE_SPI3                  FALSE
268
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
269
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
270
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
271
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
272
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
273
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
274
#define STM32_SPI_SPI1_DMA_PRIORITY         1
275
#define STM32_SPI_SPI2_DMA_PRIORITY         1
276
#define STM32_SPI_SPI3_DMA_PRIORITY         1
277
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
278
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
279
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
280
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
281

    
282
/*
283
 * ST driver system settings.
284
 */
285
#define STM32_ST_IRQ_PRIORITY               8
286
#define STM32_ST_USE_TIMER                  2
287

    
288
/*
289
 * UART driver system settings.
290
 */
291
#define STM32_UART_USE_USART1               FALSE
292
#define STM32_UART_USE_USART2               TRUE
293
#define STM32_UART_USE_USART3               FALSE
294
#define STM32_UART_USE_UART4                FALSE
295
#define STM32_UART_USE_UART5                FALSE
296
#define STM32_UART_USE_LPUART1              FALSE
297
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
298
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)
299
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
300
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
301
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
302
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
303
#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
304
#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
305
#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)
306
#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)
307
#define STM32_UART_LPUART1_RX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 7)
308
#define STM32_UART_LPUART1_TX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 6)
309
#define STM32_UART_USART1_IRQ_PRIORITY      12
310
#define STM32_UART_USART2_IRQ_PRIORITY      12
311
#define STM32_UART_USART3_IRQ_PRIORITY      12
312
#define STM32_UART_UART4_IRQ_PRIORITY       12
313
#define STM32_UART_UART5_IRQ_PRIORITY       12
314
#define STM32_UART_USART1_DMA_PRIORITY      0
315
#define STM32_UART_USART2_DMA_PRIORITY      0
316
#define STM32_UART_USART3_DMA_PRIORITY      0
317
#define STM32_UART_UART4_DMA_PRIORITY       0
318
#define STM32_UART_UART5_DMA_PRIORITY       0
319
#define STM32_UART_LPUART1_DMA_PRIORITY     0
320
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
321

    
322
/*
323
 * USB driver system settings.
324
 */
325
#define STM32_USB_USE_OTG1                  FALSE
326
#define STM32_USB_OTG1_IRQ_PRIORITY         14
327
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
328
#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
329
#define STM32_USB_OTG_THREAD_STACK_SIZE     128
330
#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
331

    
332
/*
333
 * WDG driver system settings.
334
 */
335
#define STM32_WDG_USE_IWDG                  FALSE
336

    
337
/*
338
 * QEI driver system settings.
339
 */
340
#define STM32_QEI_USE_TIM1                  FALSE
341
#define STM32_QEI_USE_TIM2                  FALSE
342
#define STM32_QEI_USE_TIM3                  FALSE
343
#define STM32_QEI_USE_TIM4                  FALSE
344
#define STM32_QEI_USE_TIM5                  FALSE
345
#define STM32_QEI_USE_TIM8                  FALSE
346

    
347
#endif /* MCUCONF_H */