Statistics
| Branch: | Tag: | Revision:

amiro-os / modules / PowerManagement_1-2 / mcuconf.h @ 4c72a54c

History | View | Annotate | Download (14.1 KB)

1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

    
19
#ifndef MCUCONF_H
20
#define MCUCONF_H
21

    
22
/*
23
 * STM32F4xx drivers configuration.
24
 * The following settings override the default settings present in
25
 * the various device driver implementation headers.
26
 * Note that the settings for each driver only have effect if the whole
27
 * driver is enabled in halconf.h.
28
 *
29
 * IRQ priorities:
30
 * 15...0       Lowest...Highest.
31
 *
32
 * DMA priorities:
33
 * 0...3        Lowest...Highest.
34
 */
35

    
36
#define STM32F4xx_MCUCONF
37

    
38
/*
39
 * Some old revisions of F4x MCU randomly chrashes with certain compiler options enabled.
40
 * This flag makes the kernel dynamically detect the MCUs ID code and CPU ID and react accordingly.
41
 * (see ChibiOS kernel: os/hal/ports/STM32/STM32F4xx/hal_lld.c)
42
 */
43
#define STM32_USE_REVISION_A_FIX
44

    
45
/*
46
 * HAL driver system settings.
47
 */
48
#define STM32_NO_INIT                       FALSE
49
#define STM32_HSI_ENABLED                   TRUE
50
#define STM32_LSI_ENABLED                   TRUE
51
#define STM32_HSE_ENABLED                   TRUE
52
#define STM32_LSE_ENABLED                   FALSE
53
#define STM32_CLOCK48_REQUIRED              TRUE
54
#define STM32_SW                            STM32_SW_PLL
55
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
56
#define STM32_PLLM_VALUE                    8
57
#define STM32_PLLN_VALUE                    336
58
#define STM32_PLLP_VALUE                    2
59
#define STM32_PLLQ_VALUE                    7
60
#define STM32_HPRE                          STM32_HPRE_DIV1
61
#define STM32_PPRE1                         STM32_PPRE1_DIV4
62
#define STM32_PPRE2                         STM32_PPRE2_DIV2
63
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
64
#define STM32_RTCPRE_VALUE                  8
65
#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
66
#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
67
#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
68
#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
69
#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
70
#define STM32_PLLI2SN_VALUE                 192
71
#define STM32_PLLI2SR_VALUE                 5
72
#define STM32_PVD_ENABLE                    FALSE
73
#define STM32_PLS                           STM32_PLS_LEV0
74
#define STM32_BKPRAM_ENABLE                 FALSE
75

    
76
/*
77
 * IRQ system settings.
78
 */
79
#define STM32_IRQ_EXTI0_PRIORITY            6
80
#define STM32_IRQ_EXTI1_PRIORITY            6
81
#define STM32_IRQ_EXTI2_PRIORITY            6
82
#define STM32_IRQ_EXTI3_PRIORITY            6
83
#define STM32_IRQ_EXTI4_PRIORITY            6
84
#define STM32_IRQ_EXTI5_9_PRIORITY          6
85
#define STM32_IRQ_EXTI10_15_PRIORITY        6
86
#define STM32_IRQ_EXTI16_PRIORITY           6
87
#define STM32_IRQ_EXTI17_PRIORITY           15
88
#define STM32_IRQ_EXTI18_PRIORITY           6
89
#define STM32_IRQ_EXTI19_PRIORITY           6
90
#define STM32_IRQ_EXTI20_PRIORITY           6
91
#define STM32_IRQ_EXTI21_PRIORITY           15
92
#define STM32_IRQ_EXTI22_PRIORITY           15
93

    
94
/*
95
 * ADC driver system settings.
96
 */
97
#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
98
#define STM32_ADC_USE_ADC1                  TRUE
99
#define STM32_ADC_USE_ADC2                  FALSE
100
#define STM32_ADC_USE_ADC3                  FALSE
101
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
102
#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
103
#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
104
#define STM32_ADC_ADC1_DMA_PRIORITY         2
105
#define STM32_ADC_ADC2_DMA_PRIORITY         2
106
#define STM32_ADC_ADC3_DMA_PRIORITY         2
107
#define STM32_ADC_IRQ_PRIORITY              6
108
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
109
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
110
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
111

    
112
/*
113
 * CAN driver system settings.
114
 */
115
#define STM32_CAN_USE_CAN1                  TRUE
116
#define STM32_CAN_USE_CAN2                  FALSE
117
#define STM32_CAN_CAN1_IRQ_PRIORITY         11
118
#define STM32_CAN_CAN2_IRQ_PRIORITY         11
119

    
120
/*
121
 * DAC driver system settings.
122
 */
123
#define STM32_DAC_DUAL_MODE                 FALSE
124
#define STM32_DAC_USE_DAC1_CH1              FALSE
125
#define STM32_DAC_USE_DAC1_CH2              FALSE
126
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
127
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
128
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
129
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
130
#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
131
#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)
132

    
133
/*
134
 * GPT driver system settings.
135
 */
136
#define STM32_GPT_USE_TIM1                  FALSE
137
#define STM32_GPT_USE_TIM2                  FALSE
138
#define STM32_GPT_USE_TIM3                  FALSE
139
#define STM32_GPT_USE_TIM4                  FALSE
140
#define STM32_GPT_USE_TIM5                  FALSE
141
#define STM32_GPT_USE_TIM6                  FALSE
142
#define STM32_GPT_USE_TIM7                  FALSE
143
#define STM32_GPT_USE_TIM8                  FALSE
144
#define STM32_GPT_USE_TIM9                  FALSE
145
#define STM32_GPT_USE_TIM11                 FALSE
146
#define STM32_GPT_USE_TIM12                 FALSE
147
#define STM32_GPT_USE_TIM14                 FALSE
148
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
149
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
150
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
151
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
152
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
153
#define STM32_GPT_TIM6_IRQ_PRIORITY         7
154
#define STM32_GPT_TIM7_IRQ_PRIORITY         7
155
#define STM32_GPT_TIM8_IRQ_PRIORITY         7
156
#define STM32_GPT_TIM9_IRQ_PRIORITY         7
157
#define STM32_GPT_TIM11_IRQ_PRIORITY        7
158
#define STM32_GPT_TIM12_IRQ_PRIORITY        7
159
#define STM32_GPT_TIM14_IRQ_PRIORITY        7
160

    
161
/*
162
 * I2C driver system settings.
163
 */
164
#define STM32_I2C_USE_I2C1                  TRUE
165
#define STM32_I2C_USE_I2C2                  TRUE
166
#define STM32_I2C_USE_I2C3                  FALSE
167
#define STM32_I2C_BUSY_TIMEOUT              50
168
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
169
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
170
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
171
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
172
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
173
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
174
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
175
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
176
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
177
#define STM32_I2C_I2C1_DMA_PRIORITY         3
178
#define STM32_I2C_I2C2_DMA_PRIORITY         3
179
#define STM32_I2C_I2C3_DMA_PRIORITY         3
180
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
181

    
182
/*
183
 * I2S driver system settings.
184
 */
185
#define STM32_I2S_USE_SPI2                  FALSE
186
#define STM32_I2S_USE_SPI3                  FALSE
187
#define STM32_I2S_SPI2_IRQ_PRIORITY         10
188
#define STM32_I2S_SPI3_IRQ_PRIORITY         10
189
#define STM32_I2S_SPI2_DMA_PRIORITY         1
190
#define STM32_I2S_SPI3_DMA_PRIORITY         1
191
#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
192
#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
193
#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
194
#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
195
#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
196

    
197
/*
198
 * ICU driver system settings.
199
 */
200
#define STM32_ICU_USE_TIM1                  FALSE
201
#define STM32_ICU_USE_TIM2                  FALSE
202
#define STM32_ICU_USE_TIM3                  FALSE
203
#define STM32_ICU_USE_TIM4                  FALSE
204
#define STM32_ICU_USE_TIM5                  FALSE
205
#define STM32_ICU_USE_TIM8                  FALSE
206
#define STM32_ICU_USE_TIM9                  FALSE
207
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
208
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
209
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
210
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
211
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
212
#define STM32_ICU_TIM8_IRQ_PRIORITY         7
213
#define STM32_ICU_TIM9_IRQ_PRIORITY         7
214

    
215
/*
216
 * MAC driver system settings.
217
 */
218
#define STM32_MAC_TRANSMIT_BUFFERS          2
219
#define STM32_MAC_RECEIVE_BUFFERS           4
220
#define STM32_MAC_BUFFERS_SIZE              1522
221
#define STM32_MAC_PHY_TIMEOUT               100
222
#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
223
#define STM32_MAC_ETH1_IRQ_PRIORITY         13
224
#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
225

    
226
/*
227
 * PWM driver system settings.
228
 */
229
#define STM32_PWM_USE_ADVANCED              FALSE
230
#define STM32_PWM_USE_TIM1                  FALSE
231
#define STM32_PWM_USE_TIM2                  FALSE
232
#define STM32_PWM_USE_TIM3                  TRUE
233
#define STM32_PWM_USE_TIM4                  FALSE
234
#define STM32_PWM_USE_TIM5                  FALSE
235
#define STM32_PWM_USE_TIM8                  FALSE
236
#define STM32_PWM_USE_TIM9                  FALSE
237
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
238
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
239
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
240
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
241
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
242
#define STM32_PWM_TIM8_IRQ_PRIORITY         7
243
#define STM32_PWM_TIM9_IRQ_PRIORITY         7
244

    
245
/*
246
 * SDC driver system settings.
247
 */
248
#define STM32_SDC_SDIO_DMA_PRIORITY         3
249
#define STM32_SDC_SDIO_IRQ_PRIORITY         9
250
#define STM32_SDC_WRITE_TIMEOUT_MS          1000
251
#define STM32_SDC_READ_TIMEOUT_MS           1000
252
#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
253
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
254
#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
255

    
256
/*
257
 * SERIAL driver system settings.
258
 */
259
#define STM32_SERIAL_USE_USART1             TRUE
260
#define STM32_SERIAL_USE_USART2             FALSE
261
#define STM32_SERIAL_USE_USART3             FALSE
262
#define STM32_SERIAL_USE_UART4              FALSE
263
#define STM32_SERIAL_USE_UART5              FALSE
264
#define STM32_SERIAL_USE_USART6             FALSE
265
#define STM32_SERIAL_USART1_PRIORITY        12
266
#define STM32_SERIAL_USART2_PRIORITY        12
267
#define STM32_SERIAL_USART3_PRIORITY        12
268
#define STM32_SERIAL_UART4_PRIORITY         12
269
#define STM32_SERIAL_UART5_PRIORITY         12
270
#define STM32_SERIAL_USART6_PRIORITY        12
271

    
272
/*
273
 * SPI driver system settings.
274
 */
275
#define STM32_SPI_USE_SPI1                  TRUE
276
#define STM32_SPI_USE_SPI2                  FALSE
277
#define STM32_SPI_USE_SPI3                  FALSE
278
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
279
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
280
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
281
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
282
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
283
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
284
#define STM32_SPI_SPI1_DMA_PRIORITY         1
285
#define STM32_SPI_SPI2_DMA_PRIORITY         1
286
#define STM32_SPI_SPI3_DMA_PRIORITY         1
287
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
288
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
289
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
290
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
291

    
292
/*
293
 * ST driver system settings.
294
 */
295
#define STM32_ST_IRQ_PRIORITY               8
296
#define STM32_ST_USE_TIMER                  2
297

    
298
/*
299
 * UART driver system settings.
300
 */
301
#define STM32_UART_USE_USART1               FALSE
302
#define STM32_UART_USE_USART2               TRUE
303
#define STM32_UART_USE_USART3               TRUE
304
#define STM32_UART_USE_UART4                FALSE
305
#define STM32_UART_USE_UART5                FALSE
306
#define STM32_UART_USE_USART6               FALSE
307
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
308
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
309
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
310
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
311
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
312
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
313
#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
314
#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
315
#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
316
#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
317
#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
318
#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
319
#define STM32_UART_USART1_IRQ_PRIORITY      12
320
#define STM32_UART_USART2_IRQ_PRIORITY      12
321
#define STM32_UART_USART3_IRQ_PRIORITY      12
322
#define STM32_UART_UART4_IRQ_PRIORITY       12
323
#define STM32_UART_UART5_IRQ_PRIORITY       12
324
#define STM32_UART_USART6_IRQ_PRIORITY      12
325
#define STM32_UART_USART1_DMA_PRIORITY      0
326
#define STM32_UART_USART2_DMA_PRIORITY      0
327
#define STM32_UART_USART3_DMA_PRIORITY      0
328
#define STM32_UART_UART4_DMA_PRIORITY       0
329
#define STM32_UART_UART5_DMA_PRIORITY       0
330
#define STM32_UART_USART6_DMA_PRIORITY      0
331
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
332

    
333
/*
334
 * USB driver system settings.
335
 */
336
#define STM32_USB_USE_OTG1                  FALSE
337
#define STM32_USB_USE_OTG2                  FALSE
338
#define STM32_USB_OTG1_IRQ_PRIORITY         14
339
#define STM32_USB_OTG2_IRQ_PRIORITY         14
340
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
341
#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
342
#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
343
#define STM32_USB_OTG_THREAD_STACK_SIZE     128
344
#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
345

    
346
/*
347
 * WDG driver system settings.
348
 */
349
#define STM32_WDG_USE_IWDG                  FALSE
350

    
351
#endif /* MCUCONF_H */