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amiro-os / modules / DiWheelDrive_1-1 / board.h @ b010278f

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1 e545e620 Thomas Schöpping
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3 84f0ce9e Thomas Schöpping
Copyright (C) 2016..2019  Thomas Schöpping et al.
4 e545e620 Thomas Schöpping

5
This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
9

10
This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
14

15
You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
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19 53710ca3 Marc Rothmann
/**
20 37bacabf Thomas Schöpping
 * @file
21 53710ca3 Marc Rothmann
 * @brief   DiWheeDrive v1.1 Board specific macros.
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 *
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 * @addtogroup diwheeldrive_board
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 * @{
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 */
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27 6ff06bbf Thomas Schöpping
#ifndef BOARD_H
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#define BOARD_H
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/*
31 043cdf33 Thomas Schöpping
 * Setup for AMiRo DiWheelDrive v1.1 board.
32 e545e620 Thomas Schöpping
 */
33
34
/*
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 * Board identifier.
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 */
37 3cb82b1a Thomas Schöpping
#define BOARD_DIWHEELDRIVE_1_1
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#define BOARD_NAME              "AMiRo DiWheelDrive v1.1"
39 e545e620 Thomas Schöpping
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/*
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 * Board oscillators-related settings.
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 * NOTE: LSE not fitted.
43
 */
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK                0U
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#endif
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48
#if !defined(STM32_HSECLK)
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#define STM32_HSECLK                8000000U
50
#endif
51
52
/*
53
 * Board voltages.
54
 * Required for performance limits calculation.
55
 */
56
#define STM32_VDD                   330U
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58
/*
59
 * MCU type as defined in the ST header.
60
 */
61
#define STM32F103xE
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63
/*
64
 * IO pins assignments.
65
 */
66
#define GPIOA_WKUP                  0U
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#define GPIOA_LED                   1U
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#define GPIOA_DRIVE_PWM1A           2U
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#define GPIOA_DRIVE_PWM1B           3U
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#define GPIOA_PIN4                  4U
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#define GPIOA_MOTION_SCLK           5U
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#define GPIOA_MOTION_MISO           6U
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#define GPIOA_MOTION_MOSI           7U
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#define GPIOA_PIN8                  8U
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#define GPIOA_PROG_RX               9U
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#define GPIOA_PROG_TX               10U
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#define GPIOA_CAN_RX                11U
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#define GPIOA_CAN_TX                12U
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#define GPIOA_SWDIO                 13U
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#define GPIOA_SWCLK                 14U
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#define GPIOA_DRIVE_PWM2B           15U
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#define GPIOB_PIN0                  0U
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#define GPIOB_DRIVE_SENSE2          1U
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#define GPIOB_POWER_EN              2U
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#define GPIOB_DRIVE_PWM2A           3U
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#define GPIOB_PIN4                  4U
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#define GPIOB_COMPASS_DRDY          5U
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#define GPIOB_DRIVE_ENC1A           6U
90
#define GPIOB_DRIVE_ENC1B           7U
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#define GPIOB_COMPASS_SCL           8U
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#define GPIOB_COMPASS_SDA           9U
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#define GPIOB_IR_SCL                10U
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#define GPIOB_IR_SDA                11U
95
#define GPIOB_IR_INT                12U
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#define GPIOB_GYRO_DRDY             13U
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#define GPIOB_SYS_UART_UP           14U
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#define GPIOB_ACCEL_INT_N           15U
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100
#define GPIOC_DRIVE_SENSE1          0U
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#define GPIOC_SYS_INT_N             1U
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#define GPIOC_PIN2                  2U
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#define GPIOC_PATH_DCSTAT           3U
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#define GPIOC_PIN4                  4U
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#define GPIOC_PATH_DCEN             5U
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#define GPIOC_DRIVE_ENC2B           6U
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#define GPIOC_DRIVE_ENC2A           7U
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#define GPIOC_SYS_PD_N              8U
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#define GPIOC_SYS_REG_EN            9U
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#define GPIOC_SYS_UART_RX           10U
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#define GPIOC_SYS_UART_TX           11U
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#define GPIOC_PIN12                 12U
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#define GPIOC_ACCEL_SS_N            13U
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#define GPIOC_GYRO_SS_N             14U
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#define GPIOC_PIN15                 15U
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#define GPIOD_OSC_IN                0U
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#define GPIOD_OSC_OUT               1U
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#define GPIOD_SYS_WARMRST_N         2U
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#define GPIOD_PIN3                  3U
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#define GPIOD_PIN4                  4U
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#define GPIOD_PIN5                  5U
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#define GPIOD_PIN6                  6U
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#define GPIOD_PIN7                  7U
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#define GPIOD_PIN8                  8U
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#define GPIOD_PIN9                  9U
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#define GPIOD_PIN10                 10U
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#define GPIOD_PIN11                 11U
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#define GPIOD_PIN12                 12U
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#define GPIOD_PIN13                 13U
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#define GPIOD_PIN14                 14U
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#define GPIOD_PIN15                 15U
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#define GPIOE_PIN0                  0U
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#define GPIOE_PIN1                  1U
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#define GPIOE_PIN2                  2U
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#define GPIOE_PIN3                  3U
138
#define GPIOE_PIN4                  4U
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#define GPIOE_PIN5                  5U
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#define GPIOE_PIN6                  6U
141
#define GPIOE_PIN7                  7U
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#define GPIOE_PIN8                  8U
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#define GPIOE_PIN9                  9U
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#define GPIOE_PIN10                 10U
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#define GPIOE_PIN11                 11U
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#define GPIOE_PIN12                 12U
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#define GPIOE_PIN13                 13U
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#define GPIOE_PIN14                 14U
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#define GPIOE_PIN15                 15U
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151
#define GPIOF_PIN0                  0U
152
#define GPIOF_PIN1                  1U
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#define GPIOF_PIN2                  2U
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#define GPIOF_PIN3                  3U
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#define GPIOF_PIN4                  4U
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#define GPIOF_PIN5                  5U
157
#define GPIOF_PIN6                  6U
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#define GPIOF_PIN7                  7U
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#define GPIOF_PIN8                  8U
160
#define GPIOF_PIN9                  9U
161
#define GPIOF_PIN10                 10U
162
#define GPIOF_PIN11                 11U
163
#define GPIOF_PIN12                 12U
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#define GPIOF_PIN13                 13U
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#define GPIOF_PIN14                 14U
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#define GPIOF_PIN15                 15U
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168
#define GPIOG_PIN0                  0U
169
#define GPIOG_PIN1                  1U
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#define GPIOG_PIN2                  2U
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#define GPIOG_PIN3                  3U
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#define GPIOG_PIN4                  4U
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#define GPIOG_PIN5                  5U
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#define GPIOG_PIN6                  6U
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#define GPIOG_PIN7                  7U
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#define GPIOG_PIN8                  8U
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#define GPIOG_PIN9                  9U
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#define GPIOG_PIN10                 10U
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#define GPIOG_PIN11                 11U
180
#define GPIOG_PIN12                 12U
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#define GPIOG_PIN13                 13U
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#define GPIOG_PIN14                 14U
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#define GPIOG_PIN15                 15U
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185
/*
186
 * IO lines assignments.
187
 */
188
#define LINE_WKUP                   PAL_LINE(GPIOA, GPIOA_WKUP)
189
#define LINE_LED                    PAL_LINE(GPIOA, GPIOA_LED)
190
#define LINE_DRIVE_PWM1A            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A)
191
#define LINE_DRIVE_PWM1B            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B)
192
#define LINE_MOTION_SCLK            PAL_LINE(GPIOA, GPIOA_MOTION_SCLK)
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#define LINE_MOTION_MISO            PAL_LINE(GPIOA, GPIOA_MOTION_MISO)
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#define LINE_MOTION_MOSI            PAL_LINE(GPIOA, GPIOA_MOTION_MOSI)
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#define LINE_PROG_RX                PAL_LINE(GPIOA, GPIOA_PROG_RX)
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#define LINE_PROG_TX                PAL_LINE(GPIOA, GPIOA_PROG_TX)
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#define LINE_CAN_RX                 PAL_LINE(GPIOA, GPIOA_CAN_RX)
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#define LINE_CAN_TX                 PAL_LINE(GPIOA, GPIOA_CAN_TX)
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#define LINE_SWDIO                  PAL_LINE(GPIOA, GPIOA_SWDIO)
200
#define LINE_SWCLK                  PAL_LINE(GPIOA, GPIOA_SWCLK)
201
#define LINE_DRIVE_PWM2B            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B)
202
203
#define LINE_DRIVE_SENSE2           PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2)
204
#define LINE_POWER_EN               PAL_LINE(GPIOB, GPIOB_POWER_EN)
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#define LINE_DRIVE_PWM2A            PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A)
206
#define LINE_COMPASS_DRDY           PAL_LINE(GPIOB, GPIOB_COMPASS_DRDY)
207
#define LINE_DRIVE_ENC1A            PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A)
208
#define LINE_DRIVE_ENC1B            PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B)
209
#define LINE_COMPASS_SCL            PAL_LINE(GPIOB, GPIOB_COMPASS_SCL)
210
#define LINE_COMPASS_SDA            PAL_LINE(GPIOB, GPIOB_COMPASS_SDA)
211
#define LINE_IR_SCL                 PAL_LINE(GPIOB, GPIOB_IR_SCL)
212
#define LINE_IR_SDA                 PAL_LINE(GPIOB, GPIOB_IR_SDA)
213
#define LINE_IR_INT                 PAL_LINE(GPIOB, GPIOB_IR_INT)
214
#define LINE_GYRO_DRDY              PAL_LINE(GPIOB, GPIOB_GYRO_DRDY)
215
#define LINE_SYS_UART_UP            PAL_LINE(GPIOB, GPIOB_SYS_UART_UP)
216
#define LINE_ACCEL_INT_N            PAL_LINE(GPIOB, GPIOB_ACCEL_INT_N)
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218
#define LINE_DRIVE_SENSE1           PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1)
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#define LINE_SYS_INT_N              PAL_LINE(GPIOC, GPIOC_SYS_INT_N)
220
#define LINE_PATH_DCSTAT            PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT)
221
#define LINE_PATH_DCEN              PAL_LINE(GPIOC, GPIOC_PATH_DCEN)
222
#define LINE_DRIVE_ENC2B            PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B)
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#define LINE_DRIVE_ENC2A            PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A)
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#define LINE_SYS_PD_N               PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
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#define LINE_SYS_REG_EN             PAL_LINE(GPIOC, GPIOC_SYS_REG_EN)
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#define LINE_SYS_UART_RX            PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
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#define LINE_SYS_UART_TX            PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
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#define LINE_ACCEL_SS_N             PAL_LINE(GPIOC, GPIOC_ACCEL_SS_N)
229
#define LINE_GYRO_SS_N              PAL_LINE(GPIOC, GPIOC_GYRO_SS_N)
230
231
#define LINE_OSC_IN                 PAL_LINE(GPIOD, GPIOD_OSC_IN)
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#define LINE_OSC_OUT                PAL_LINE(GPIOD, GPIOD_OSC_OUT)
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#define LINE_SYS_WARMRST_N          PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N)
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235
/*
236
 * I/O ports initial setup, this configuration is established soon after reset
237
 * in the initialization code.
238
 * Please refer to the STM32 Reference Manual for details.
239
 */
240
#define PIN_MODE_INPUT              0U
241
#define PIN_MODE_OUTPUT_2M          2U
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#define PIN_MODE_OUTPUT_10M         1U
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#define PIN_MODE_OUTPUT_50M         3U
244
#define PIN_CNF_INPUT_ANALOG        0U
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#define PIN_CNF_INPUT_FLOATING      1U
246
#define PIN_CNF_INPUT_PULLX         2U
247
#define PIN_CNF_OUTPUT_PUSHPULL     0U
248
#define PIN_CNF_OUTPUT_OPENDRAIN    1U
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#define PIN_CNF_ALTERNATE_PUSHPULL  2U
250
#define PIN_CNF_ALTERNATE_OPENDRAIN 3U
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#define PIN_CR(pin, mode, cnf)      (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U))
252
#define PIN_ODR_LOW(n)              (0U << (n))
253
#define PIN_ODR_HIGH(n)             (1U << (n))
254 37bacabf Thomas Schöpping
#define PIN_IGNORE(n)               (1U << (n))
255 e545e620 Thomas Schöpping
256
/*
257
 * GPIOA setup:
258
 *
259
 * PA0  - WKUP                      (input floating)
260
 * PA1  - LED                       (output opendrain high 50MHz)
261
 * PA2  - DRIVE_PWM1A               (alternate pushpull 50MHz)
262
 * PA3  - DRIVE_PWM1B               (alternate pushpull 50MHz)
263
 * PA4  - PIN4                      (input floating)
264
 * PA5  - MOTION_SCLK               (alternate pushpull 50MHz)
265
 * PA6  - MOTION_MISO               (input pullup)
266
 * PA7  - MOTION_MOSI               (alternate pushpull 50MHz)
267
 * PA8  - PIN8                      (input floating)
268
 * PA9  - PROG_RX                   (alternate pushpull 50MHz)
269
 * PA10 - PROG_TX                   (input pullup)
270
 * PA11 - CAN_RX                    (input pullup)
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 * PA12 - CAN_TX                    (alternate pushpull 50MHz)
272 e545e620 Thomas Schöpping
 * PA13 - SWDIO                     (input pullup)
273
 * PA14 - SWCLK                     (input pullup)
274
 * PA15 - DRIVE_PWM2B               (alternate pushpull 50MHz)
275
 */
276 37bacabf Thomas Schöpping
#define VAL_GPIOAIGN                (PIN_IGNORE(GPIOA_LED)) & 0
277 e545e620 Thomas Schöpping
#define VAL_GPIOACRL                (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |            \
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                                     PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
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                                     PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
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                                     PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_MOTION_SCLK, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
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                                     PIN_CR(GPIOA_MOTION_MISO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |              \
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                                     PIN_CR(GPIOA_MOTION_MOSI, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL))
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#define VAL_GPIOACRH                (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |      \
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                                     PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                  \
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                                     PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                   \
289 933df08e Thomas Schöpping
                                     PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |       \
290 e545e620 Thomas Schöpping
                                     PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                    \
291
                                     PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                    \
292
                                     PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL))
293
#define VAL_GPIOAODR                (PIN_ODR_HIGH(GPIOA_WKUP) |                                                    \
294
                                     PIN_ODR_HIGH(GPIOA_LED) |                                                     \
295
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) |                                             \
296
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) |                                             \
297
                                     PIN_ODR_LOW(GPIOA_PIN4) |                                                     \
298
                                     PIN_ODR_HIGH(GPIOA_MOTION_SCLK) |                                             \
299
                                     PIN_ODR_HIGH(GPIOA_MOTION_MISO) |                                             \
300
                                     PIN_ODR_HIGH(GPIOA_MOTION_MOSI) |                                             \
301
                                     PIN_ODR_LOW(GPIOA_PIN8) |                                                     \
302
                                     PIN_ODR_HIGH(GPIOA_PROG_RX) |                                                 \
303
                                     PIN_ODR_HIGH(GPIOA_PROG_TX) |                                                 \
304
                                     PIN_ODR_HIGH(GPIOA_CAN_RX) |                                                  \
305
                                     PIN_ODR_HIGH(GPIOA_CAN_TX) |                                                  \
306
                                     PIN_ODR_HIGH(GPIOA_SWDIO) |                                                   \
307
                                     PIN_ODR_HIGH(GPIOA_SWCLK) |                                                   \
308
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B))
309
310
/*
311
 * GPIOB setup:
312
 *
313
 * PB0  - PIN0                      (input floating)
314
 * PB1  - DRIVE_SENSE2              (input analog)
315
 * PB2  - POWER_EN                  (output pushpull low 50MHz)
316
 * PB3  - DRIVE_PWM2A               (alternate pushpull 50MHz)
317
 * PB4  - PIN4                      (input floating)
318
 * PB5  - COMPASS_DRDY              (input pullup)
319
 * PB6  - DRIVE_ENC1A               (input floating)
320
 * PB7  - DRIVE_ENC1B               (input floating)
321
 * PB8  - COMPASS_SCL               (alternate opendrain 50MHz)
322
 * PB9  - COMPASS_SDA               (alternate opendrain 50MHz)
323
 * PB10 - IR_SCL                    (alternate opendrain 50MHz)
324
 * PB11 - IR_SDA                    (alternate opendrain 50MHz)
325 542939ea Thomas Schöpping
 * PB12 - IR_INT                    (input floating)
326 e545e620 Thomas Schöpping
 * PB13 - GYRO_DRDY                 (input pullup)
327
 * PB14 - SYS_UART_UP               (output opendrain high 50MHz)
328
 * PB15 - ACCEL_INT_N               (input pullup)
329
 */
330 37bacabf Thomas Schöpping
#define VAL_GPIOBIGN                (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0
331 e545e620 Thomas Schöpping
#define VAL_GPIOBCRL                (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
332
                                     PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) |            \
333
                                     PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |        \
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                                     PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
335
                                     PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
336
                                     PIN_CR(GPIOB_COMPASS_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |             \
337
                                     PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
338
                                     PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
339
#define VAL_GPIOBCRH                (PIN_CR(GPIOB_COMPASS_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \
340
                                     PIN_CR(GPIOB_COMPASS_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \
341
                                     PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |      \
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                                     PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |      \
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                                     PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                \
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                                     PIN_CR(GPIOB_GYRO_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                \
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                                     PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |    \
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                                     PIN_CR(GPIOB_ACCEL_INT_N, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX))
347
#define VAL_GPIOBODR                (PIN_ODR_LOW(GPIOB_PIN0) |                                                     \
348
                                     PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) |                                            \
349
                                     PIN_ODR_LOW(GPIOB_POWER_EN) |                                                 \
350
                                     PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) |                                             \
351
                                     PIN_ODR_LOW(GPIOB_PIN4) |                                                     \
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                                     PIN_ODR_HIGH(GPIOB_COMPASS_DRDY) |                                            \
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                                     PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) |                                             \
354
                                     PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) |                                             \
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                                     PIN_ODR_HIGH(GPIOB_COMPASS_SCL) |                                             \
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                                     PIN_ODR_HIGH(GPIOB_COMPASS_SDA) |                                             \
357
                                     PIN_ODR_HIGH(GPIOB_IR_SCL) |                                                  \
358
                                     PIN_ODR_HIGH(GPIOB_IR_SDA) |                                                  \
359
                                     PIN_ODR_HIGH(GPIOB_IR_INT) |                                                  \
360
                                     PIN_ODR_HIGH(GPIOB_GYRO_DRDY) |                                               \
361
                                     PIN_ODR_HIGH(GPIOB_SYS_UART_UP) |                                             \
362
                                     PIN_ODR_HIGH(GPIOB_ACCEL_INT_N))
363
364
/*
365
 * GPIOC setup:
366
 *
367
 * PC0  - DRIVE_SENSE1              (input analog)
368
 * PC1  - SYS_INT_N                 (output opendrain low 50MHz)
369
 * PC2  - PIN2                      (input floating)
370
 * PC3  - PATH_DCSTAT               (input floating)
371
 * PC4  - PIN4                      (input floating)
372
 * PC5  - PATH_DCEN                 (output pushpull low 50MHz)
373
 * PC6  - DRIVE_ENC2B               (input floating)
374
 * PC7  - DRIVE_ENC2A               (input floating)
375
 * PC8  - SYS_PD_N                  (output opendrain high 50MHz)
376
 * PC9  - SYS_REG_EN                (input floating)
377
 * PC10 - SYS_UART_RX               (input floating)
378
 * PC11 - SYS_UART_TX               (input floating)
379
 * PC12 - PIN12                     (input pullup)
380
 * PC13 - ACCEL_SS_N                (output pushpull high 50MHz)
381
 * PC14 - GYRO_SS_N                 (output pushpull high 50MHz)
382
 * PC15 - PIN15                     (input floating)
383
 */
384 37bacabf Thomas Schöpping
#define VAL_GPIOCIGN                (PIN_IGNORE(GPIOC_SYS_INT_N) |                                                 \
385
                                     PIN_IGNORE(GPIOC_SYS_PD_N)) & 0
386 e545e620 Thomas Schöpping
#define VAL_GPIOCCRL                (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) |            \
387 37bacabf Thomas Schöpping
                                     PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |      \
388 e545e620 Thomas Schöpping
                                     PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
389
                                     PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
390
                                     PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
391
                                     PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |       \
392
                                     PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
393
                                     PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
394
#define VAL_GPIOCCRH                (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |       \
395
                                     PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |            \
396
                                     PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
397
                                     PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
398
                                     PIN_CR(GPIOC_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
399
                                     PIN_CR(GPIOC_ACCEL_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |      \
400
                                     PIN_CR(GPIOC_GYRO_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |       \
401
                                     PIN_CR(GPIOC_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
402
#define VAL_GPIOCODR                (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) |                                            \
403
                                     PIN_ODR_LOW(GPIOC_SYS_INT_N) |                                                \
404
                                     PIN_ODR_LOW(GPIOC_PIN2) |                                                     \
405
                                     PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) |                                             \
406
                                     PIN_ODR_LOW(GPIOC_PIN4) |                                                     \
407
                                     PIN_ODR_LOW(GPIOC_PATH_DCEN) |                                                \
408
                                     PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) |                                             \
409
                                     PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) |                                             \
410
                                     PIN_ODR_HIGH(GPIOC_SYS_PD_N) |                                                \
411
                                     PIN_ODR_HIGH(GPIOC_SYS_REG_EN) |                                              \
412
                                     PIN_ODR_HIGH(GPIOC_SYS_UART_RX) |                                             \
413
                                     PIN_ODR_HIGH(GPIOC_SYS_UART_TX) |                                             \
414
                                     PIN_ODR_LOW(GPIOC_PIN12) |                                                    \
415
                                     PIN_ODR_HIGH(GPIOC_ACCEL_SS_N) |                                              \
416
                                     PIN_ODR_HIGH(GPIOC_GYRO_SS_N) |                                               \
417
                                     PIN_ODR_LOW(GPIOC_PIN15))
418
419
/*
420
 * GPIOD setup:
421
 *
422
 * PD0  - OSC_IN                    (input floating)
423
 * PD1  - OSC_OUT                   (input floating)
424
 * PD2  - SYS_WARMRST_N             (output opendrain high 50MHz)
425
 * PD3  - PIN3                      (input floating)
426
 * PD4  - PIN4                      (input floating)
427
 * PD5  - PIN5                      (input floating)
428
 * PD6  - PIN6                      (input floating)
429
 * PD7  - PIN7                      (input floating)
430
 * PD8  - PIN8                      (input floating)
431
 * PD9  - PIN9                      (input floating)
432
 * PD10 - PIN10                     (input floating)
433
 * PD11 - PIN11                     (input floating)
434
 * PD12 - PIN12                     (input floating)
435
 * PD13 - PIN13                     (input floating)
436
 * PD14 - PIN14                     (input floating)
437
 * PD15 - PIN15                     (input floating)
438
 */
439 37bacabf Thomas Schöpping
#define VAL_GPIODIGN                0
440 e545e620 Thomas Schöpping
#define VAL_GPIODCRL                (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                \
441
                                     PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |               \
442
                                     PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |  \
443
                                     PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
444
                                     PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
445
                                     PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
446
                                     PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
447
                                     PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
448
#define VAL_GPIODCRH                (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
449
                                     PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
450
                                     PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
451
                                     PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
452
                                     PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
453
                                     PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
454
                                     PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
455
                                     PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
456
#define VAL_GPIODODR                (PIN_ODR_HIGH(GPIOD_OSC_IN) |                                                  \
457
                                     PIN_ODR_HIGH(GPIOD_OSC_OUT) |                                                 \
458
                                     PIN_ODR_HIGH(GPIOD_SYS_WARMRST_N) |                                           \
459
                                     PIN_ODR_LOW(GPIOD_PIN3) |                                                     \
460
                                     PIN_ODR_LOW(GPIOD_PIN4) |                                                     \
461
                                     PIN_ODR_LOW(GPIOD_PIN5) |                                                     \
462
                                     PIN_ODR_LOW(GPIOD_PIN6) |                                                     \
463
                                     PIN_ODR_LOW(GPIOD_PIN7) |                                                     \
464
                                     PIN_ODR_LOW(GPIOD_PIN8) |                                                     \
465
                                     PIN_ODR_LOW(GPIOD_PIN9) |                                                     \
466
                                     PIN_ODR_LOW(GPIOD_PIN10) |                                                    \
467
                                     PIN_ODR_LOW(GPIOD_PIN11) |                                                    \
468
                                     PIN_ODR_LOW(GPIOD_PIN12) |                                                    \
469
                                     PIN_ODR_LOW(GPIOD_PIN13) |                                                    \
470
                                     PIN_ODR_LOW(GPIOD_PIN14) |                                                    \
471
                                     PIN_ODR_LOW(GPIOD_PIN15))
472
473
/*
474
 * GPIOE setup:
475
 *
476
 * PE0  - PIN0                      (input floating)
477
 * PE1  - PIN1                      (input floating)
478
 * PE2  - PIN2                      (input floating)
479
 * PE3  - PIN3                      (input floating)
480
 * PE4  - PIN4                      (input floating)
481
 * PE5  - PIN5                      (input floating)
482
 * PE6  - PIN6                      (input floating)
483
 * PE7  - PIN7                      (input floating)
484
 * PE8  - PIN8                      (input floating)
485
 * PE9  - PIN9                      (input floating)
486
 * PE10 - PIN10                     (input floating)
487
 * PE11 - PIN11                     (input floating)
488
 * PE12 - PIN12                     (input floating)
489
 * PE13 - PIN13                     (input floating)
490
 * PE14 - PIN14                     (input floating)
491
 * PE15 - PIN15                     (input floating)
492
 */
493 37bacabf Thomas Schöpping
#define VAL_GPIOEIGN                0
494 e545e620 Thomas Schöpping
#define VAL_GPIOECRL                (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
495
                                     PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
496
                                     PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
497
                                     PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
498
                                     PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
499
                                     PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
500
                                     PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
501
                                     PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
502
#define VAL_GPIOECRH                (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
503
                                     PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
504
                                     PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
505
                                     PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
506
                                     PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
507
                                     PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
508
                                     PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
509
                                     PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
510
#define VAL_GPIOEODR                (PIN_ODR_LOW(GPIOE_PIN0) |                                                     \
511
                                     PIN_ODR_LOW(GPIOE_PIN1) |                                                     \
512
                                     PIN_ODR_LOW(GPIOE_PIN2) |                                                     \
513
                                     PIN_ODR_LOW(GPIOE_PIN3) |                                                     \
514
                                     PIN_ODR_LOW(GPIOE_PIN4) |                                                     \
515
                                     PIN_ODR_LOW(GPIOE_PIN5) |                                                     \
516
                                     PIN_ODR_LOW(GPIOE_PIN6) |                                                     \
517
                                     PIN_ODR_LOW(GPIOE_PIN7) |                                                     \
518
                                     PIN_ODR_LOW(GPIOE_PIN8) |                                                     \
519
                                     PIN_ODR_LOW(GPIOE_PIN9) |                                                     \
520
                                     PIN_ODR_LOW(GPIOE_PIN10) |                                                    \
521
                                     PIN_ODR_LOW(GPIOE_PIN11) |                                                    \
522
                                     PIN_ODR_LOW(GPIOE_PIN12) |                                                    \
523
                                     PIN_ODR_LOW(GPIOE_PIN13) |                                                    \
524
                                     PIN_ODR_LOW(GPIOE_PIN14) |                                                    \
525
                                     PIN_ODR_LOW(GPIOE_PIN15))
526
527
/*
528
 * GPIOF setup:
529
 *
530
 * PF0  - PIN0                      (input floating)
531
 * PF1  - PIN1                      (input floating)
532
 * PF2  - PIN2                      (input floating)
533
 * PF3  - PIN3                      (input floating)
534
 * PF4  - PIN4                      (input floating)
535
 * PF5  - PIN5                      (input floating)
536
 * PF6  - PIN6                      (input floating)
537
 * PF7  - PIN7                      (input floating)
538
 * PF8  - PIN8                      (input floating)
539
 * PF9  - PIN9                      (input floating)
540
 * PF10 - PIN10                     (input floating)
541
 * PF11 - PIN11                     (input floating)
542
 * PF12 - PIN12                     (input floating)
543
 * PF13 - PIN13                     (input floating)
544
 * PF14 - PIN14                     (input floating)
545
 * PF15 - PIN15                     (input floating)
546
 */
547 37bacabf Thomas Schöpping
#define VAL_GPIOFIGN                0
548 e545e620 Thomas Schöpping
#define VAL_GPIOFCRL                (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
549
                                     PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
550
                                     PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
551
                                     PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
552
                                     PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
553
                                     PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
554
                                     PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
555
                                     PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
556
#define VAL_GPIOFCRH                (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
557
                                     PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
558
                                     PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
559
                                     PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
560
                                     PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
561
                                     PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
562
                                     PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
563
                                     PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
564
#define VAL_GPIOFODR                (PIN_ODR_LOW(GPIOF_PIN0) |                                                     \
565
                                     PIN_ODR_LOW(GPIOF_PIN1) |                                                     \
566
                                     PIN_ODR_LOW(GPIOF_PIN2) |                                                     \
567
                                     PIN_ODR_LOW(GPIOF_PIN3) |                                                     \
568
                                     PIN_ODR_LOW(GPIOF_PIN4) |                                                     \
569
                                     PIN_ODR_LOW(GPIOF_PIN5) |                                                     \
570
                                     PIN_ODR_LOW(GPIOF_PIN6) |                                                     \
571
                                     PIN_ODR_LOW(GPIOF_PIN7) |                                                     \
572
                                     PIN_ODR_LOW(GPIOF_PIN8) |                                                     \
573
                                     PIN_ODR_LOW(GPIOF_PIN9) |                                                     \
574
                                     PIN_ODR_LOW(GPIOF_PIN10) |                                                    \
575
                                     PIN_ODR_LOW(GPIOF_PIN11) |                                                    \
576
                                     PIN_ODR_LOW(GPIOF_PIN12) |                                                    \
577
                                     PIN_ODR_LOW(GPIOF_PIN13) |                                                    \
578
                                     PIN_ODR_LOW(GPIOF_PIN14) |                                                    \
579
                                     PIN_ODR_LOW(GPIOF_PIN15))
580
581
/*
582
 * GPIOG setup:
583
 *
584
 * PG0  - PIN0                      (input floating)
585
 * PG1  - PIN1                      (input floating)
586
 * PG2  - PIN2                      (input floating)
587
 * PG3  - PIN3                      (input floating)
588
 * PG4  - PIN4                      (input floating)
589
 * PG5  - PIN5                      (input floating)
590
 * PG6  - PIN6                      (input floating)
591
 * PG7  - PIN7                      (input floating)
592
 * PG8  - PIN8                      (input floating)
593
 * PG9  - PIN9                      (input floating)
594
 * PG10 - PIN10                     (input floating)
595
 * PG11 - PIN11                     (input floating)
596
 * PG12 - PIN12                     (input floating)
597
 * PG13 - PIN13                     (input floating)
598
 * PG14 - PIN14                     (input floating)
599
 * PG15 - PIN15                     (input floating)
600
 */
601 37bacabf Thomas Schöpping
#define VAL_GPIOGIGN                0
602 e545e620 Thomas Schöpping
#define VAL_GPIOGCRL                (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
603
                                     PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
604
                                     PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
605
                                     PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
606
                                     PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
607
                                     PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
608
                                     PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
609
                                     PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
610
#define VAL_GPIOGCRH                (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
611
                                     PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
612
                                     PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
613
                                     PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
614
                                     PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
615
                                     PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
616
                                     PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
617
                                     PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
618
#define VAL_GPIOGODR                (PIN_ODR_LOW(GPIOG_PIN0) |                                                     \
619
                                     PIN_ODR_LOW(GPIOG_PIN1) |                                                     \
620
                                     PIN_ODR_LOW(GPIOG_PIN2) |                                                     \
621
                                     PIN_ODR_LOW(GPIOG_PIN3) |                                                     \
622
                                     PIN_ODR_LOW(GPIOG_PIN4) |                                                     \
623
                                     PIN_ODR_LOW(GPIOG_PIN5) |                                                     \
624
                                     PIN_ODR_LOW(GPIOG_PIN6) |                                                     \
625
                                     PIN_ODR_LOW(GPIOG_PIN7) |                                                     \
626
                                     PIN_ODR_LOW(GPIOG_PIN8) |                                                     \
627
                                     PIN_ODR_LOW(GPIOG_PIN9) |                                                     \
628
                                     PIN_ODR_LOW(GPIOG_PIN10) |                                                    \
629
                                     PIN_ODR_LOW(GPIOG_PIN11) |                                                    \
630
                                     PIN_ODR_LOW(GPIOG_PIN12) |                                                    \
631
                                     PIN_ODR_LOW(GPIOG_PIN13) |                                                    \
632
                                     PIN_ODR_LOW(GPIOG_PIN14) |                                                    \
633
                                     PIN_ODR_LOW(GPIOG_PIN15))
634
635
#if !defined(_FROM_ASM_)
636
#ifdef __cplusplus
637
extern "C" {
638
#endif
639
  void boardInit(void);
640
#ifdef __cplusplus
641
}
642
#endif
643
#endif /* _FROM_ASM_ */
644
645 6ff06bbf Thomas Schöpping
#endif /* BOARD_H */
646 53710ca3 Marc Rothmann
647
/** @} */