amiro-os / modules / DiWheelDrive_1-1 / board.h @ b010278f
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| 1 | e545e620 | Thomas Schöpping | /*
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| 2 | AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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| 3 | 84f0ce9e | Thomas Schöpping | Copyright (C) 2016..2019 Thomas Schöpping et al.
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| 4 | e545e620 | Thomas Schöpping | |
| 5 | This program is free software: you can redistribute it and/or modify
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| 6 | it under the terms of the GNU General Public License as published by
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| 7 | the Free Software Foundation, either version 3 of the License, or
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| 8 | (at your option) any later version.
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| 9 | |||
| 10 | This program is distributed in the hope that it will be useful,
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| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 13 | GNU General Public License for more details.
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| 14 | |||
| 15 | You should have received a copy of the GNU General Public License
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| 16 | along with this program. If not, see <http://www.gnu.org/licenses/>.
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| 17 | */
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| 18 | |||
| 19 | 53710ca3 | Marc Rothmann | /**
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| 20 | 37bacabf | Thomas Schöpping | * @file
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| 21 | 53710ca3 | Marc Rothmann | * @brief DiWheeDrive v1.1 Board specific macros.
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| 22 | *
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| 23 | * @addtogroup diwheeldrive_board
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| 24 | * @{
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| 25 | */
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| 26 | |||
| 27 | 6ff06bbf | Thomas Schöpping | #ifndef BOARD_H
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| 28 | #define BOARD_H
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| 29 | e545e620 | Thomas Schöpping | |
| 30 | /*
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| 31 | 043cdf33 | Thomas Schöpping | * Setup for AMiRo DiWheelDrive v1.1 board.
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| 32 | e545e620 | Thomas Schöpping | */
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| 33 | |||
| 34 | /*
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| 35 | * Board identifier.
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| 36 | */
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| 37 | 3cb82b1a | Thomas Schöpping | #define BOARD_DIWHEELDRIVE_1_1
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| 38 | #define BOARD_NAME "AMiRo DiWheelDrive v1.1" |
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| 39 | e545e620 | Thomas Schöpping | |
| 40 | /*
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| 41 | * Board oscillators-related settings.
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| 42 | * NOTE: LSE not fitted.
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| 43 | */
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| 44 | #if !defined(STM32_LSECLK)
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| 45 | #define STM32_LSECLK 0U |
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| 46 | #endif
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| 47 | |||
| 48 | #if !defined(STM32_HSECLK)
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| 49 | #define STM32_HSECLK 8000000U |
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| 50 | #endif
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| 51 | |||
| 52 | /*
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| 53 | * Board voltages.
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| 54 | * Required for performance limits calculation.
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| 55 | */
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| 56 | #define STM32_VDD 330U |
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| 57 | |||
| 58 | /*
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| 59 | * MCU type as defined in the ST header.
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| 60 | */
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| 61 | #define STM32F103xE
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| 62 | |||
| 63 | /*
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| 64 | * IO pins assignments.
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| 65 | */
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| 66 | #define GPIOA_WKUP 0U |
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| 67 | #define GPIOA_LED 1U |
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| 68 | #define GPIOA_DRIVE_PWM1A 2U |
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| 69 | #define GPIOA_DRIVE_PWM1B 3U |
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| 70 | #define GPIOA_PIN4 4U |
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| 71 | #define GPIOA_MOTION_SCLK 5U |
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| 72 | #define GPIOA_MOTION_MISO 6U |
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| 73 | #define GPIOA_MOTION_MOSI 7U |
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| 74 | #define GPIOA_PIN8 8U |
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| 75 | #define GPIOA_PROG_RX 9U |
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| 76 | #define GPIOA_PROG_TX 10U |
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| 77 | #define GPIOA_CAN_RX 11U |
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| 78 | #define GPIOA_CAN_TX 12U |
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| 79 | #define GPIOA_SWDIO 13U |
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| 80 | #define GPIOA_SWCLK 14U |
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| 81 | #define GPIOA_DRIVE_PWM2B 15U |
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| 82 | |||
| 83 | #define GPIOB_PIN0 0U |
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| 84 | #define GPIOB_DRIVE_SENSE2 1U |
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| 85 | #define GPIOB_POWER_EN 2U |
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| 86 | #define GPIOB_DRIVE_PWM2A 3U |
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| 87 | #define GPIOB_PIN4 4U |
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| 88 | #define GPIOB_COMPASS_DRDY 5U |
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| 89 | #define GPIOB_DRIVE_ENC1A 6U |
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| 90 | #define GPIOB_DRIVE_ENC1B 7U |
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| 91 | #define GPIOB_COMPASS_SCL 8U |
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| 92 | #define GPIOB_COMPASS_SDA 9U |
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| 93 | #define GPIOB_IR_SCL 10U |
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| 94 | #define GPIOB_IR_SDA 11U |
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| 95 | #define GPIOB_IR_INT 12U |
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| 96 | #define GPIOB_GYRO_DRDY 13U |
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| 97 | #define GPIOB_SYS_UART_UP 14U |
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| 98 | #define GPIOB_ACCEL_INT_N 15U |
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| 99 | |||
| 100 | #define GPIOC_DRIVE_SENSE1 0U |
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| 101 | #define GPIOC_SYS_INT_N 1U |
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| 102 | #define GPIOC_PIN2 2U |
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| 103 | #define GPIOC_PATH_DCSTAT 3U |
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| 104 | #define GPIOC_PIN4 4U |
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| 105 | #define GPIOC_PATH_DCEN 5U |
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| 106 | #define GPIOC_DRIVE_ENC2B 6U |
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| 107 | #define GPIOC_DRIVE_ENC2A 7U |
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| 108 | #define GPIOC_SYS_PD_N 8U |
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| 109 | #define GPIOC_SYS_REG_EN 9U |
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| 110 | #define GPIOC_SYS_UART_RX 10U |
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| 111 | #define GPIOC_SYS_UART_TX 11U |
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| 112 | #define GPIOC_PIN12 12U |
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| 113 | #define GPIOC_ACCEL_SS_N 13U |
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| 114 | #define GPIOC_GYRO_SS_N 14U |
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| 115 | #define GPIOC_PIN15 15U |
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| 116 | |||
| 117 | #define GPIOD_OSC_IN 0U |
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| 118 | #define GPIOD_OSC_OUT 1U |
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| 119 | #define GPIOD_SYS_WARMRST_N 2U |
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| 120 | #define GPIOD_PIN3 3U |
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| 121 | #define GPIOD_PIN4 4U |
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| 122 | #define GPIOD_PIN5 5U |
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| 123 | #define GPIOD_PIN6 6U |
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| 124 | #define GPIOD_PIN7 7U |
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| 125 | #define GPIOD_PIN8 8U |
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| 126 | #define GPIOD_PIN9 9U |
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| 127 | #define GPIOD_PIN10 10U |
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| 128 | #define GPIOD_PIN11 11U |
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| 129 | #define GPIOD_PIN12 12U |
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| 130 | #define GPIOD_PIN13 13U |
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| 131 | #define GPIOD_PIN14 14U |
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| 132 | #define GPIOD_PIN15 15U |
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| 133 | |||
| 134 | #define GPIOE_PIN0 0U |
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| 135 | #define GPIOE_PIN1 1U |
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| 136 | #define GPIOE_PIN2 2U |
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| 137 | #define GPIOE_PIN3 3U |
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| 138 | #define GPIOE_PIN4 4U |
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| 139 | #define GPIOE_PIN5 5U |
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| 140 | #define GPIOE_PIN6 6U |
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| 141 | #define GPIOE_PIN7 7U |
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| 142 | #define GPIOE_PIN8 8U |
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| 143 | #define GPIOE_PIN9 9U |
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| 144 | #define GPIOE_PIN10 10U |
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| 145 | #define GPIOE_PIN11 11U |
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| 146 | #define GPIOE_PIN12 12U |
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| 147 | #define GPIOE_PIN13 13U |
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| 148 | #define GPIOE_PIN14 14U |
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| 149 | #define GPIOE_PIN15 15U |
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| 150 | |||
| 151 | #define GPIOF_PIN0 0U |
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| 152 | #define GPIOF_PIN1 1U |
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| 153 | #define GPIOF_PIN2 2U |
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| 154 | #define GPIOF_PIN3 3U |
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| 155 | #define GPIOF_PIN4 4U |
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| 156 | #define GPIOF_PIN5 5U |
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| 157 | #define GPIOF_PIN6 6U |
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| 158 | #define GPIOF_PIN7 7U |
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| 159 | #define GPIOF_PIN8 8U |
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| 160 | #define GPIOF_PIN9 9U |
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| 161 | #define GPIOF_PIN10 10U |
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| 162 | #define GPIOF_PIN11 11U |
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| 163 | #define GPIOF_PIN12 12U |
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| 164 | #define GPIOF_PIN13 13U |
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| 165 | #define GPIOF_PIN14 14U |
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| 166 | #define GPIOF_PIN15 15U |
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| 167 | |||
| 168 | #define GPIOG_PIN0 0U |
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| 169 | #define GPIOG_PIN1 1U |
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| 170 | #define GPIOG_PIN2 2U |
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| 171 | #define GPIOG_PIN3 3U |
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| 172 | #define GPIOG_PIN4 4U |
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| 173 | #define GPIOG_PIN5 5U |
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| 174 | #define GPIOG_PIN6 6U |
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| 175 | #define GPIOG_PIN7 7U |
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| 176 | #define GPIOG_PIN8 8U |
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| 177 | #define GPIOG_PIN9 9U |
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| 178 | #define GPIOG_PIN10 10U |
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| 179 | #define GPIOG_PIN11 11U |
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| 180 | #define GPIOG_PIN12 12U |
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| 181 | #define GPIOG_PIN13 13U |
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| 182 | #define GPIOG_PIN14 14U |
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| 183 | #define GPIOG_PIN15 15U |
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| 184 | |||
| 185 | /*
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| 186 | * IO lines assignments.
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| 187 | */
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| 188 | #define LINE_WKUP PAL_LINE(GPIOA, GPIOA_WKUP)
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| 189 | #define LINE_LED PAL_LINE(GPIOA, GPIOA_LED)
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| 190 | #define LINE_DRIVE_PWM1A PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A)
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| 191 | #define LINE_DRIVE_PWM1B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B)
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| 192 | #define LINE_MOTION_SCLK PAL_LINE(GPIOA, GPIOA_MOTION_SCLK)
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| 193 | #define LINE_MOTION_MISO PAL_LINE(GPIOA, GPIOA_MOTION_MISO)
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| 194 | #define LINE_MOTION_MOSI PAL_LINE(GPIOA, GPIOA_MOTION_MOSI)
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| 195 | #define LINE_PROG_RX PAL_LINE(GPIOA, GPIOA_PROG_RX)
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| 196 | #define LINE_PROG_TX PAL_LINE(GPIOA, GPIOA_PROG_TX)
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| 197 | #define LINE_CAN_RX PAL_LINE(GPIOA, GPIOA_CAN_RX)
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| 198 | #define LINE_CAN_TX PAL_LINE(GPIOA, GPIOA_CAN_TX)
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| 199 | #define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO)
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| 200 | #define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK)
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| 201 | #define LINE_DRIVE_PWM2B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B)
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| 202 | |||
| 203 | #define LINE_DRIVE_SENSE2 PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2)
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| 204 | #define LINE_POWER_EN PAL_LINE(GPIOB, GPIOB_POWER_EN)
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| 205 | #define LINE_DRIVE_PWM2A PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A)
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| 206 | #define LINE_COMPASS_DRDY PAL_LINE(GPIOB, GPIOB_COMPASS_DRDY)
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| 207 | #define LINE_DRIVE_ENC1A PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A)
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| 208 | #define LINE_DRIVE_ENC1B PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B)
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| 209 | #define LINE_COMPASS_SCL PAL_LINE(GPIOB, GPIOB_COMPASS_SCL)
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| 210 | #define LINE_COMPASS_SDA PAL_LINE(GPIOB, GPIOB_COMPASS_SDA)
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| 211 | #define LINE_IR_SCL PAL_LINE(GPIOB, GPIOB_IR_SCL)
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| 212 | #define LINE_IR_SDA PAL_LINE(GPIOB, GPIOB_IR_SDA)
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| 213 | #define LINE_IR_INT PAL_LINE(GPIOB, GPIOB_IR_INT)
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| 214 | #define LINE_GYRO_DRDY PAL_LINE(GPIOB, GPIOB_GYRO_DRDY)
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| 215 | #define LINE_SYS_UART_UP PAL_LINE(GPIOB, GPIOB_SYS_UART_UP)
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| 216 | #define LINE_ACCEL_INT_N PAL_LINE(GPIOB, GPIOB_ACCEL_INT_N)
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| 217 | |||
| 218 | #define LINE_DRIVE_SENSE1 PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1)
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| 219 | #define LINE_SYS_INT_N PAL_LINE(GPIOC, GPIOC_SYS_INT_N)
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| 220 | #define LINE_PATH_DCSTAT PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT)
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| 221 | #define LINE_PATH_DCEN PAL_LINE(GPIOC, GPIOC_PATH_DCEN)
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| 222 | #define LINE_DRIVE_ENC2B PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B)
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| 223 | #define LINE_DRIVE_ENC2A PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A)
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| 224 | #define LINE_SYS_PD_N PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
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| 225 | #define LINE_SYS_REG_EN PAL_LINE(GPIOC, GPIOC_SYS_REG_EN)
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| 226 | #define LINE_SYS_UART_RX PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
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| 227 | #define LINE_SYS_UART_TX PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
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| 228 | #define LINE_ACCEL_SS_N PAL_LINE(GPIOC, GPIOC_ACCEL_SS_N)
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| 229 | #define LINE_GYRO_SS_N PAL_LINE(GPIOC, GPIOC_GYRO_SS_N)
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| 230 | |||
| 231 | #define LINE_OSC_IN PAL_LINE(GPIOD, GPIOD_OSC_IN)
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| 232 | #define LINE_OSC_OUT PAL_LINE(GPIOD, GPIOD_OSC_OUT)
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| 233 | #define LINE_SYS_WARMRST_N PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N)
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| 234 | |||
| 235 | /*
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| 236 | * I/O ports initial setup, this configuration is established soon after reset
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| 237 | * in the initialization code.
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| 238 | * Please refer to the STM32 Reference Manual for details.
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| 239 | */
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| 240 | #define PIN_MODE_INPUT 0U |
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| 241 | #define PIN_MODE_OUTPUT_2M 2U |
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| 242 | #define PIN_MODE_OUTPUT_10M 1U |
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| 243 | #define PIN_MODE_OUTPUT_50M 3U |
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| 244 | #define PIN_CNF_INPUT_ANALOG 0U |
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| 245 | #define PIN_CNF_INPUT_FLOATING 1U |
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| 246 | #define PIN_CNF_INPUT_PULLX 2U |
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| 247 | #define PIN_CNF_OUTPUT_PUSHPULL 0U |
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| 248 | #define PIN_CNF_OUTPUT_OPENDRAIN 1U |
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| 249 | #define PIN_CNF_ALTERNATE_PUSHPULL 2U |
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| 250 | #define PIN_CNF_ALTERNATE_OPENDRAIN 3U |
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| 251 | #define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
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| 252 | #define PIN_ODR_LOW(n) (0U << (n)) |
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| 253 | #define PIN_ODR_HIGH(n) (1U << (n)) |
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| 254 | 37bacabf | Thomas Schöpping | #define PIN_IGNORE(n) (1U << (n)) |
| 255 | e545e620 | Thomas Schöpping | |
| 256 | /*
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| 257 | * GPIOA setup:
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| 258 | *
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| 259 | * PA0 - WKUP (input floating)
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| 260 | * PA1 - LED (output opendrain high 50MHz)
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| 261 | * PA2 - DRIVE_PWM1A (alternate pushpull 50MHz)
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| 262 | * PA3 - DRIVE_PWM1B (alternate pushpull 50MHz)
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| 263 | * PA4 - PIN4 (input floating)
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| 264 | * PA5 - MOTION_SCLK (alternate pushpull 50MHz)
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| 265 | * PA6 - MOTION_MISO (input pullup)
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| 266 | * PA7 - MOTION_MOSI (alternate pushpull 50MHz)
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| 267 | * PA8 - PIN8 (input floating)
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| 268 | * PA9 - PROG_RX (alternate pushpull 50MHz)
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| 269 | * PA10 - PROG_TX (input pullup)
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| 270 | * PA11 - CAN_RX (input pullup)
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| 271 | 933df08e | Thomas Schöpping | * PA12 - CAN_TX (alternate pushpull 50MHz)
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| 272 | e545e620 | Thomas Schöpping | * PA13 - SWDIO (input pullup)
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| 273 | * PA14 - SWCLK (input pullup)
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| 274 | * PA15 - DRIVE_PWM2B (alternate pushpull 50MHz)
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| 275 | */
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| 276 | 37bacabf | Thomas Schöpping | #define VAL_GPIOAIGN (PIN_IGNORE(GPIOA_LED)) & 0 |
| 277 | e545e620 | Thomas Schöpping | #define VAL_GPIOACRL (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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| 278 | PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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| 279 | PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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| 280 | PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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| 281 | PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 282 | PIN_CR(GPIOA_MOTION_SCLK, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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| 283 | PIN_CR(GPIOA_MOTION_MISO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 284 | PIN_CR(GPIOA_MOTION_MOSI, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
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| 285 | #define VAL_GPIOACRH (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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| 286 | PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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| 287 | PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 288 | PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 289 | 933df08e | Thomas Schöpping | PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
| 290 | e545e620 | Thomas Schöpping | PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
| 291 | PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 292 | PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
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| 293 | #define VAL_GPIOAODR (PIN_ODR_HIGH(GPIOA_WKUP) | \
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| 294 | PIN_ODR_HIGH(GPIOA_LED) | \ |
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| 295 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) | \ |
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| 296 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) | \ |
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| 297 | PIN_ODR_LOW(GPIOA_PIN4) | \ |
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| 298 | PIN_ODR_HIGH(GPIOA_MOTION_SCLK) | \ |
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| 299 | PIN_ODR_HIGH(GPIOA_MOTION_MISO) | \ |
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| 300 | PIN_ODR_HIGH(GPIOA_MOTION_MOSI) | \ |
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| 301 | PIN_ODR_LOW(GPIOA_PIN8) | \ |
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| 302 | PIN_ODR_HIGH(GPIOA_PROG_RX) | \ |
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| 303 | PIN_ODR_HIGH(GPIOA_PROG_TX) | \ |
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| 304 | PIN_ODR_HIGH(GPIOA_CAN_RX) | \ |
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| 305 | PIN_ODR_HIGH(GPIOA_CAN_TX) | \ |
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| 306 | PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
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| 307 | PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
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| 308 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B)) |
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| 309 | |||
| 310 | /*
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| 311 | * GPIOB setup:
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| 312 | *
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| 313 | * PB0 - PIN0 (input floating)
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| 314 | * PB1 - DRIVE_SENSE2 (input analog)
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| 315 | * PB2 - POWER_EN (output pushpull low 50MHz)
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| 316 | * PB3 - DRIVE_PWM2A (alternate pushpull 50MHz)
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| 317 | * PB4 - PIN4 (input floating)
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| 318 | * PB5 - COMPASS_DRDY (input pullup)
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| 319 | * PB6 - DRIVE_ENC1A (input floating)
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| 320 | * PB7 - DRIVE_ENC1B (input floating)
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| 321 | * PB8 - COMPASS_SCL (alternate opendrain 50MHz)
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| 322 | * PB9 - COMPASS_SDA (alternate opendrain 50MHz)
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| 323 | * PB10 - IR_SCL (alternate opendrain 50MHz)
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| 324 | * PB11 - IR_SDA (alternate opendrain 50MHz)
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| 325 | 542939ea | Thomas Schöpping | * PB12 - IR_INT (input floating)
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| 326 | e545e620 | Thomas Schöpping | * PB13 - GYRO_DRDY (input pullup)
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| 327 | * PB14 - SYS_UART_UP (output opendrain high 50MHz)
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| 328 | * PB15 - ACCEL_INT_N (input pullup)
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| 329 | */
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| 330 | 37bacabf | Thomas Schöpping | #define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
| 331 | e545e620 | Thomas Schöpping | #define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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| 332 | PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
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| 333 | PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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| 334 | PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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| 335 | PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 336 | PIN_CR(GPIOB_COMPASS_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 337 | PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 338 | PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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| 339 | #define VAL_GPIOBCRH (PIN_CR(GPIOB_COMPASS_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \
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| 340 | PIN_CR(GPIOB_COMPASS_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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| 341 | PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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| 342 | PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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| 343 | PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 344 | PIN_CR(GPIOB_GYRO_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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| 345 | PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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| 346 | PIN_CR(GPIOB_ACCEL_INT_N, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX)) |
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| 347 | #define VAL_GPIOBODR (PIN_ODR_LOW(GPIOB_PIN0) | \
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| 348 | PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) | \ |
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| 349 | PIN_ODR_LOW(GPIOB_POWER_EN) | \ |
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| 350 | PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) | \ |
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| 351 | PIN_ODR_LOW(GPIOB_PIN4) | \ |
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| 352 | PIN_ODR_HIGH(GPIOB_COMPASS_DRDY) | \ |
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| 353 | PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) | \ |
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| 354 | PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) | \ |
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| 355 | PIN_ODR_HIGH(GPIOB_COMPASS_SCL) | \ |
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| 356 | PIN_ODR_HIGH(GPIOB_COMPASS_SDA) | \ |
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| 357 | PIN_ODR_HIGH(GPIOB_IR_SCL) | \ |
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| 358 | PIN_ODR_HIGH(GPIOB_IR_SDA) | \ |
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| 359 | PIN_ODR_HIGH(GPIOB_IR_INT) | \ |
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| 360 | PIN_ODR_HIGH(GPIOB_GYRO_DRDY) | \ |
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| 361 | PIN_ODR_HIGH(GPIOB_SYS_UART_UP) | \ |
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| 362 | PIN_ODR_HIGH(GPIOB_ACCEL_INT_N)) |
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| 363 | |||
| 364 | /*
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| 365 | * GPIOC setup:
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| 366 | *
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| 367 | * PC0 - DRIVE_SENSE1 (input analog)
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| 368 | * PC1 - SYS_INT_N (output opendrain low 50MHz)
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| 369 | * PC2 - PIN2 (input floating)
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| 370 | * PC3 - PATH_DCSTAT (input floating)
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| 371 | * PC4 - PIN4 (input floating)
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| 372 | * PC5 - PATH_DCEN (output pushpull low 50MHz)
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| 373 | * PC6 - DRIVE_ENC2B (input floating)
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| 374 | * PC7 - DRIVE_ENC2A (input floating)
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| 375 | * PC8 - SYS_PD_N (output opendrain high 50MHz)
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| 376 | * PC9 - SYS_REG_EN (input floating)
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| 377 | * PC10 - SYS_UART_RX (input floating)
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| 378 | * PC11 - SYS_UART_TX (input floating)
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| 379 | * PC12 - PIN12 (input pullup)
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| 380 | * PC13 - ACCEL_SS_N (output pushpull high 50MHz)
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| 381 | * PC14 - GYRO_SS_N (output pushpull high 50MHz)
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| 382 | * PC15 - PIN15 (input floating)
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| 383 | */
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| 384 | 37bacabf | Thomas Schöpping | #define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_INT_N) | \
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| 385 | PIN_IGNORE(GPIOC_SYS_PD_N)) & 0
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| 386 | e545e620 | Thomas Schöpping | #define VAL_GPIOCCRL (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \
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| 387 | 37bacabf | Thomas Schöpping | PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 388 | e545e620 | Thomas Schöpping | PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 389 | PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 390 | PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 391 | PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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| 392 | PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 393 | PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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| 394 | #define VAL_GPIOCCRH (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \
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| 395 | PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 396 | PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 397 | PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 398 | PIN_CR(GPIOC_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 399 | PIN_CR(GPIOC_ACCEL_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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| 400 | PIN_CR(GPIOC_GYRO_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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| 401 | PIN_CR(GPIOC_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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| 402 | #define VAL_GPIOCODR (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) | \
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| 403 | PIN_ODR_LOW(GPIOC_SYS_INT_N) | \ |
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| 404 | PIN_ODR_LOW(GPIOC_PIN2) | \ |
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| 405 | PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) | \ |
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| 406 | PIN_ODR_LOW(GPIOC_PIN4) | \ |
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| 407 | PIN_ODR_LOW(GPIOC_PATH_DCEN) | \ |
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| 408 | PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) | \ |
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| 409 | PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) | \ |
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| 410 | PIN_ODR_HIGH(GPIOC_SYS_PD_N) | \ |
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| 411 | PIN_ODR_HIGH(GPIOC_SYS_REG_EN) | \ |
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| 412 | PIN_ODR_HIGH(GPIOC_SYS_UART_RX) | \ |
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| 413 | PIN_ODR_HIGH(GPIOC_SYS_UART_TX) | \ |
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| 414 | PIN_ODR_LOW(GPIOC_PIN12) | \ |
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| 415 | PIN_ODR_HIGH(GPIOC_ACCEL_SS_N) | \ |
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| 416 | PIN_ODR_HIGH(GPIOC_GYRO_SS_N) | \ |
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| 417 | PIN_ODR_LOW(GPIOC_PIN15)) |
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| 418 | |||
| 419 | /*
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| 420 | * GPIOD setup:
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| 421 | *
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| 422 | * PD0 - OSC_IN (input floating)
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| 423 | * PD1 - OSC_OUT (input floating)
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| 424 | * PD2 - SYS_WARMRST_N (output opendrain high 50MHz)
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| 425 | * PD3 - PIN3 (input floating)
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| 426 | * PD4 - PIN4 (input floating)
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| 427 | * PD5 - PIN5 (input floating)
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| 428 | * PD6 - PIN6 (input floating)
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| 429 | * PD7 - PIN7 (input floating)
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| 430 | * PD8 - PIN8 (input floating)
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| 431 | * PD9 - PIN9 (input floating)
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| 432 | * PD10 - PIN10 (input floating)
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| 433 | * PD11 - PIN11 (input floating)
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| 434 | * PD12 - PIN12 (input floating)
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| 435 | * PD13 - PIN13 (input floating)
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| 436 | * PD14 - PIN14 (input floating)
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| 437 | * PD15 - PIN15 (input floating)
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| 438 | */
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| 439 | 37bacabf | Thomas Schöpping | #define VAL_GPIODIGN 0 |
| 440 | e545e620 | Thomas Schöpping | #define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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| 441 | PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 442 | PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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| 443 | PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 444 | PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 445 | PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 446 | PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 447 | PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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| 448 | #define VAL_GPIODCRH (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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| 449 | PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 450 | PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 451 | PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 452 | PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 453 | PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 454 | PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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| 455 | PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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| 456 | #define VAL_GPIODODR (PIN_ODR_HIGH(GPIOD_OSC_IN) | \
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| 457 | PIN_ODR_HIGH(GPIOD_OSC_OUT) | \ |