amiro-os / boards / DiWheelDrive / board.h @ bc91a128
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1 | 58fe0e0b | Thomas Schöpping | #ifndef _BOARD_H_
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2 | #define _BOARD_H_
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3 | |||
4 | /*
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5 | * Setup for AMiRo DiWheelDrive board.
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6 | */
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7 | |||
8 | /*
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9 | * Board identifier.
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10 | */
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11 | #define BOARD_DI_WHEEL_DRIVE
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12 | #define BOARD_NAME "AMiRo DiWheelDrive" |
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13 | #define BOARD_VERSION "1.1" |
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14 | |||
15 | /*
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16 | * Board frequencies.
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17 | */
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18 | #define STM32_LSECLK 0 |
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19 | #define STM32_HSECLK 8000000 |
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20 | |||
21 | /*
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22 | * MCU type as defined in the ST header file stm32f1xx.h.
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23 | */
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24 | #define STM32F10X_HD
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25 | |||
26 | /*
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27 | * IO pins assignments.
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28 | */
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29 | #define GPIOA_WKUP 0 |
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30 | #define GPIOA_LED 1 |
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31 | #define GPIOA_DRIVE_PWM1A 2 |
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32 | #define GPIOA_DRIVE_PWM1B 3 |
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33 | #define GPIOA_MOTION_SCLK 5 |
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34 | #define GPIOA_MOTION_MISO 6 |
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35 | #define GPIOA_MOTION_MOSI 7 |
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36 | #define GPIOA_PROG_RX 9 |
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37 | #define GPIOA_PROG_TX 10 |
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38 | #define GPIOA_CAN_RX 11 |
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39 | #define GPIOA_CAN_TX 12 |
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40 | #define GPIOA_SWDIO 13 |
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41 | #define GPIOA_SWCLK 14 |
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42 | #define GPIOA_DRIVE_PWM2B 15 |
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43 | |||
44 | |||
45 | #define GPIOB_DRIVE_SENSE2 1 |
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46 | #define GPIOB_POWER_EN 2 |
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47 | #define GPIOB_DRIVE_PWM2A 3 |
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48 | #define GPIOB_COMPASS_DRDY 5 |
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49 | #define GPIOB_DRIVE_ENC1A 6 |
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50 | #define GPIOB_DRIVE_ENC1B 7 |
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51 | #define GPIOB_COMPASS_SCL 8 |
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52 | #define GPIOB_COMPASS_SDA 9 |
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53 | #define GPIOB_IR_SCL 10 |
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54 | #define GPIOB_IR_SDA 11 |
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55 | #define GPIOB_IR_INT 12 |
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56 | #define GPIOB_GYRO_DRDY 13 |
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57 | #define GPIOB_SYS_UART_UP 14 |
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58 | #define GPIOB_ACCEL_INT_N 15 |
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59 | |||
60 | #define GPIOC_DRIVE_SENSE1 0 |
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61 | #define GPIOC_SYS_INT_N 1 |
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62 | #define GPIOC_PATH_DCSTAT 3 |
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63 | #define GPIOC_PATH_DCEN 5 |
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64 | #define GPIOC_DRIVE_ENC2B 6 |
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65 | #define GPIOC_DRIVE_ENC2A 7 |
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66 | #define GPIOC_SYS_PD_N 8 |
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67 | #define GPIOC_SYS_REG_EN 9 |
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68 | #define GPIOC_SYS_UART_RX 10 |
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69 | #define GPIOC_SYS_UART_TX 11 |
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70 | #define GPIOC_ACCEL_SS_N 13 |
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71 | #define GPIOC_GYRO_SS_N 14 |
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72 | |||
73 | #define GPIOD_OSC_IN 0 |
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74 | #define GPIOD_OSC_OUT 1 |
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75 | #define GPIOD_SYS_WARMRST_N 2 |
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76 | |||
77 | /*
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78 | * I/O ports initial setup, this configuration is established soon after reset
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79 | * in the initialization code.
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80 | */
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81 | #define PIN_MODE_INPUT(n) (0x4U << (((n) % 8) * 4)) |
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82 | #define PIN_MODE_INPUT_PULLX(n) (0x8U << (((n) % 8) * 4)) |
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83 | #define PIN_MODE_INPUT_ANALOG(n) (0x0U << (((n) % 8) * 4)) |
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84 | /* Push Pull output 50MHz */
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85 | #define PIN_MODE_OUTPUT_PUSHPULL(n) (0x3U << (((n) % 8) * 4)) |
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86 | /* Open Drain output 50MHz */
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87 | #define PIN_MODE_OUTPUT_OPENDRAIN(n) (0x7U << (((n) % 8) * 4)) |
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88 | /* Alternate Push Pull output 50MHz */
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89 | #define PIN_MODE_ALTERNATE_PUSHPULL(n) (0xbU << (((n) % 8) * 4)) |
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90 | /* Alternate Open Drain output 50MHz */
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91 | #define PIN_MODE_ALTERNATE_OPENDRAIN(n) (0xfU << (((n) % 8) * 4)) |
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92 | |||
93 | /*
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94 | * Port A setup.
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95 | */
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96 | #define VAL_GPIOACRL (PIN_MODE_INPUT(GPIOA_WKUP) | \
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97 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOA_LED) | \ |
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98 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1A) | \ |
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99 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1B) | \ |
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100 | PIN_MODE_INPUT_PULLX(4) | \
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101 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_SCLK) | \ |
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102 | PIN_MODE_INPUT_PULLX(GPIOA_MOTION_MISO) | \ |
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103 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_MOSI)) |
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104 | #define VAL_GPIOACRH (PIN_MODE_INPUT_PULLX(8) | \ |
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105 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_PROG_RX) | \ |
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106 | PIN_MODE_INPUT_PULLX(GPIOA_PROG_TX) | \ |
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107 | PIN_MODE_INPUT_PULLX(GPIOA_CAN_RX) | \ |
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108 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_CAN_TX) | \ |
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109 | PIN_MODE_INPUT_PULLX(GPIOA_SWDIO) | \ |
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110 | PIN_MODE_INPUT_PULLX(GPIOA_SWCLK) | \ |
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111 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM2B)) |
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112 | #define VAL_GPIOAODR 0xF7FF /* prevent power over CAN bug */ |
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113 | |||
114 | /*
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115 | * Port B setup.
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116 | */
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117 | #define VAL_GPIOBCRL (PIN_MODE_INPUT_PULLX(0) | \ |
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118 | PIN_MODE_INPUT_ANALOG(GPIOB_DRIVE_SENSE2) | \ |
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119 | PIN_MODE_OUTPUT_PUSHPULL(GPIOB_POWER_EN) | \ |
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120 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOB_DRIVE_PWM2A) | \ |
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121 | PIN_MODE_INPUT_PULLX(4) | \
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122 | PIN_MODE_INPUT_PULLX(GPIOB_COMPASS_DRDY) | \ |
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123 | PIN_MODE_INPUT(GPIOB_DRIVE_ENC1A) | \ |
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124 | PIN_MODE_INPUT(GPIOB_DRIVE_ENC1B)) |
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125 | #define VAL_GPIOBCRH (PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SCL) | \
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126 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SDA) | \ |
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127 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SCL) | \ |
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128 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SDA) | \ |
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129 | PIN_MODE_INPUT(GPIOB_IR_INT) | \ |
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130 | PIN_MODE_INPUT_PULLX(GPIOB_GYRO_DRDY) | \ |
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131 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOB_SYS_UART_UP) | \ |
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132 | PIN_MODE_INPUT_PULLX(GPIOB_ACCEL_INT_N)) |
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133 | #define VAL_GPIOBODR 0xFFFB /* initially the motors are not powered */ |
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134 | |||
135 | /*
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136 | * Port C setup.
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137 | */
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138 | #define VAL_GPIOCCRL (PIN_MODE_INPUT_ANALOG(GPIOC_DRIVE_SENSE1) | \
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139 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_INT_N) | \ |
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140 | PIN_MODE_INPUT_PULLX(2) | \
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141 | PIN_MODE_INPUT(GPIOC_PATH_DCSTAT) | \ |
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142 | PIN_MODE_INPUT_PULLX(4) | \
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143 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_PATH_DCEN) | \ |
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144 | PIN_MODE_INPUT(GPIOC_DRIVE_ENC2B) | \ |
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145 | PIN_MODE_INPUT(GPIOC_DRIVE_ENC2A)) |
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146 | #define VAL_GPIOCCRH (PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_PD_N) | \
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147 | PIN_MODE_INPUT(GPIOC_SYS_REG_EN) | \ |
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148 | PIN_MODE_INPUT(GPIOC_SYS_UART_RX) | \ |
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149 | PIN_MODE_INPUT(GPIOC_SYS_UART_TX) | \ |
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150 | PIN_MODE_INPUT_PULLX(12) | \
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151 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_ACCEL_SS_N) | \ |
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152 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_GYRO_SS_N) | \ |
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153 | PIN_MODE_INPUT_PULLX(15))
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154 | #define VAL_GPIOCODR 0xFFDD /* initially charging via the pins is disabled and SYSNIN_N indicates that the OS is busy */ |
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155 | |||
156 | /*
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157 | * Port D setup.
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158 | */
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159 | #define VAL_GPIODCRL (PIN_MODE_INPUT(GPIOD_OSC_IN) | \
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160 | PIN_MODE_INPUT(GPIOD_OSC_OUT) | \ |
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161 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOD_SYS_WARMRST_N) | \ |
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162 | PIN_MODE_INPUT_PULLX(3) | \
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163 | PIN_MODE_INPUT_PULLX(4) | \
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164 | PIN_MODE_INPUT_PULLX(5) | \
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165 | PIN_MODE_INPUT_PULLX(6) | \
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166 | PIN_MODE_INPUT_PULLX(7))
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167 | #define VAL_GPIODCRH 0x88888888 |
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168 | #define VAL_GPIODODR 0xFFFF |
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169 | |||
170 | /*
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171 | * Port E setup.
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172 | */
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173 | #define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ |
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174 | #define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ |
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175 | #define VAL_GPIOEODR 0xFFFF |
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176 | |||
177 | /*
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178 | * Port F setup.
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179 | */
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180 | #define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ |
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181 | #define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ |
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182 | #define VAL_GPIOFODR 0xFFFF |
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183 | |||
184 | /*
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185 | * Port G setup.
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186 | */
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187 | #define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ |
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188 | #define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ |
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189 | #define VAL_GPIOGODR 0xFFFF |
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190 | |||
191 | #if !defined(_FROM_ASM_)
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192 | #ifdef __cplusplus
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193 | extern "C" { |
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194 | #endif
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195 | void boardInit(void); |
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196 | void boardWriteIoPower(const uint8_t value); |
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197 | void boardWriteLed(int value); |
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198 | void boardRequestShutdown(void); |
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199 | void boardStandby(void); |
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200 | void boardWakeup(void); |
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201 | b4885314 | Thomas Schöpping | void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad); |
202 | 58fe0e0b | Thomas Schöpping | #ifdef __cplusplus
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203 | } |
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204 | #endif
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205 | #endif /* _FROM_ASM_ */ |
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206 | |||
207 | #endif /* _BOARD_H_ */ |