amiro-os / boards / PowerManagement / board.h @ bdac5bec
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| 1 | 58fe0e0b | Thomas Schöpping | #ifndef _BOARD_H_
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| 2 | #define _BOARD_H_
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| 3 | |||
| 4 | /*
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| 5 | * Setup for AMiRo PowerManagement board.
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| 6 | */
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| 7 | |||
| 8 | /*
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| 9 | * Board identifier.
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| 10 | */
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| 11 | #define BOARD_POWER_MANAGEMENT
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| 12 | #define BOARD_NAME "AMiRo PowerManagement" |
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| 13 | #define BOARD_VERSION "1.1" |
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| 14 | |||
| 15 | /*
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| 16 | * Board frequencies.
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| 17 | */
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| 18 | #define STM32_LSECLK 0 |
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| 19 | #define STM32_HSECLK 8000000 |
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| 20 | |||
| 21 | /*
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| 22 | * Board voltages.
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| 23 | * Required for performance limits calculation.
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| 24 | */
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| 25 | #define STM32_VDD 330 |
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| 26 | |||
| 27 | /*
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| 28 | * MCU type as defined in the ST header file stm32f4xx.h.
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| 29 | */
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| 30 | #define STM32F40_41xxx
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| 31 | |||
| 32 | /*
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| 33 | * IO pins assignments.
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| 34 | */
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| 35 | #define GPIOA_WKUP 0 |
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| 36 | #define GPIOA_SYS_UART_TX 2 |
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| 37 | #define GPIOA_SYS_UART_RX 3 |
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| 38 | #define GPIOA_SYS_SPI_SS0_N 4 |
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| 39 | #define GPIOA_SYS_SPI_SCLK 5 |
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| 40 | #define GPIOA_SYS_SPI_MISO 6 |
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| 41 | #define GPIOA_SYS_SPI_MOSI 7 |
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| 42 | #define GPIOA_SYS_REG_EN 8 |
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| 43 | #define GPIOA_PROG_RX 9 |
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| 44 | #define GPIOA_PROG_TX 10 |
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| 45 | #define GPIOA_CAN_RX 11 |
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| 46 | #define GPIOA_CAN_TX 12 |
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| 47 | #define GPIOA_SYS_SPI_SS1_N 15 |
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| 48 | |||
| 49 | #define GPIOB_IR_INT1_N 0 |
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| 50 | #define GPIOB_VSYS_SENSE 1 |
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| 51 | #define GPIOB_POWER_EN 2 |
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| 52 | #define GPIOB_SYS_UART_DN 3 |
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| 53 | #define GPIOB_CHARGE_STAT2A 4 |
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| 54 | #define GPIOB_BUZZER 5 |
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| 55 | #define GPIOB_GAUGE_BATLOW2 6 |
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| 56 | #define GPIOB_GAUGE_BATGD2_N 7 |
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| 57 | #define GPIOB_GAUGE_SCL2 8 |
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| 58 | #define GPIOB_GAUGE_SDA2 9 |
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| 59 | #define GPIOB_GAUGE_SCL1 10 |
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| 60 | #define GPIOB_GAUGE_SDA1 11 |
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| 61 | #define GPIOB_LED 12 |
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| 62 | #define GPIOB_BT_RTS 13 |
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| 63 | #define GPIOB_BT_CTS 14 |
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| 64 | #define GPIOB_SYS_UART_UP 15 |
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| 65 | |||
| 66 | #define GPIOC_CHARGE_STAT1A 0 |
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| 67 | #define GPIOC_GAUGE_BATLOW1 1 |
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| 68 | #define GPIOC_GAUGE_BATGD1_N 2 |
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| 69 | #define GPIOC_CHARGE_EN1_N 3 |
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| 70 | #define GPIOC_IR_INT2_N 4 |
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| 71 | #define GPIOC_TOUCH_INT_N 5 |
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| 72 | #define GPIOC_SYS_DONE 6 |
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| 73 | #define GPIOC_SYS_PROG_N 7 |
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| 74 | #define GPIOC_PATH_DC 8 |
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| 75 | #define GPIOC_SYS_SPI_DIR 9 |
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| 76 | #define GPIOC_BT_RX 10 |
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| 77 | #define GPIOC_BT_TX 11 |
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| 78 | #define GPIOC_SYS_INT_N 12 |
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| 79 | #define GPIOC_SYS_PD_N 13 |
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| 80 | #define GPIOC_SYS_WARMRST_N 14 |
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| 81 | #define GPIOC_BT_RST 15 |
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| 82 | |||
| 83 | #define GPIOD_CHARGE_EN2_N 2 |
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| 84 | |||
| 85 | #define GPIOH_OSC_IN 0 |
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| 86 | #define GPIOH_OSC_OUT 1 |
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| 87 | |||
| 88 | /*
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| 89 | * I/O ports initial setup, this configuration is established soon after reset
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| 90 | * in the initialization code.
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| 91 | */
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| 92 | #define PIN_MODE_INPUT(n) (0U << ((n) * 2)) |
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| 93 | #define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) |
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| 94 | #define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) |
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| 95 | #define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) |
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| 96 | #define PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
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| 97 | #define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
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| 98 | #define PIN_OSPEED_2M(n) (0U << ((n) * 2)) |
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| 99 | #define PIN_OSPEED_25M(n) (1U << ((n) * 2)) |
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| 100 | #define PIN_OSPEED_50M(n) (2U << ((n) * 2)) |
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| 101 | #define PIN_OSPEED_100M(n) (3U << ((n) * 2)) |
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| 102 | #define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) |
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| 103 | #define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) |
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| 104 | #define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) |
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| 105 | #define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) |
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| 106 | |||
| 107 | /*
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| 108 | * Port A setup.
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| 109 | */
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| 110 | #define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP) | \
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| 111 | PIN_MODE_INPUT(1) | \
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| 112 | PIN_MODE_ALTERNATE(GPIOA_SYS_UART_TX) | \ |
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| 113 | PIN_MODE_ALTERNATE(GPIOA_SYS_UART_RX) | \ |
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| 114 | PIN_MODE_INPUT(GPIOA_SYS_SPI_SS0_N) | \ |
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| 115 | PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_SCLK) | \ |
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| 116 | PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MOSI) | \ |
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| 117 | PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MISO) | \ |
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| 118 | PIN_MODE_INPUT(GPIOA_SYS_SPI_SS1_N) | \ |
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| 119 | PIN_MODE_ALTERNATE(GPIOA_PROG_RX) | \ |
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| 120 | PIN_MODE_ALTERNATE(GPIOA_PROG_TX) | \ |
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| 121 | PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ |
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| 122 | PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ |
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| 123 | PIN_MODE_INPUT(13) | \
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| 124 | PIN_MODE_INPUT(14) | \
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| 125 | PIN_MODE_OUTPUT(GPIOA_SYS_REG_EN)) |
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| 126 | #define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_SYS_UART_TX) | \
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| 127 | PIN_OTYPE_PUSHPULL(GPIOA_SYS_SPI_SS0_N) | \ |
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| 128 | PIN_OTYPE_PUSHPULL(GPIOA_PROG_RX) | \ |
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| 129 | PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ |
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| 130 | PIN_OTYPE_PUSHPULL(GPIOA_SYS_REG_EN)) |
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| 131 | #define VAL_GPIOA_OSPEEDR 0xFFFFFFFF |
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| 132 | #define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_WKUP) | \
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| 133 | PIN_PUDR_PULLUP(1) | \
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| 134 | PIN_PUDR_FLOATING(GPIOA_SYS_UART_TX) | \ |
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| 135 | PIN_PUDR_FLOATING(GPIOA_SYS_UART_RX) | \ |
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| 136 | PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS0_N) | \ |
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| 137 | PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SCLK) | \ |
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| 138 | PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MOSI) | \ |
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| 139 | PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MISO) | \ |
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| 140 | PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS1_N) | \ |
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| 141 | PIN_PUDR_FLOATING(GPIOA_PROG_RX) | \ |
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| 142 | PIN_PUDR_PULLUP(GPIOA_PROG_TX) | \ |
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| 143 | PIN_PUDR_FLOATING(GPIOA_CAN_RX) | \ |
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| 144 | PIN_PUDR_FLOATING(GPIOA_CAN_TX) | \ |
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| 145 | PIN_PUDR_PULLUP(13) | \
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| 146 | PIN_PUDR_PULLUP(14) | \
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| 147 | PIN_PUDR_FLOATING(GPIOA_SYS_REG_EN)) |
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| 148 | |||
| 149 | #define VAL_GPIOA_ODR 0xFFFF |
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| 150 | #define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_SYS_UART_TX, 7) | \ |
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| 151 | PIN_AFIO_AF(GPIOA_SYS_UART_RX, 7) | \
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| 152 | PIN_AFIO_AF(GPIOA_SYS_SPI_SCLK, 5) | \
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| 153 | PIN_AFIO_AF(GPIOA_SYS_SPI_MISO, 5) | \
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| 154 | PIN_AFIO_AF(GPIOA_SYS_SPI_MOSI, 5))
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| 155 | #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PROG_RX, 7) | \ |
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| 156 | PIN_AFIO_AF(GPIOA_PROG_TX, 7) | \
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| 157 | PIN_AFIO_AF(GPIOA_CAN_RX, 9) | \
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| 158 | PIN_AFIO_AF(GPIOA_CAN_TX, 9))
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| 159 | |||
| 160 | /*
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| 161 | * Port B setup.
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| 162 | */
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| 163 | #define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_IR_INT1_N) | \
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| 164 | PIN_MODE_ANALOG(GPIOB_VSYS_SENSE) | \ |
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| 165 | PIN_MODE_OUTPUT(GPIOB_POWER_EN) | \ |
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| 166 | PIN_MODE_OUTPUT(GPIOB_SYS_UART_DN) | \ |
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| 167 | PIN_MODE_INPUT(GPIOB_CHARGE_STAT2A) | \ |
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| 168 | PIN_MODE_ALTERNATE(GPIOB_BUZZER) | \ |
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| 169 | PIN_MODE_INPUT(GPIOB_GAUGE_BATLOW2) | \ |
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| 170 | PIN_MODE_INPUT(GPIOB_GAUGE_BATGD2_N) | \ |
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| 171 | PIN_MODE_ALTERNATE(GPIOB_GAUGE_SCL2) | \ |
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| 172 | PIN_MODE_ALTERNATE(GPIOB_GAUGE_SDA2) | \ |
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| 173 | PIN_MODE_ALTERNATE(GPIOB_GAUGE_SCL1) | \ |
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| 174 | PIN_MODE_ALTERNATE(GPIOB_GAUGE_SDA1) | \ |
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| 175 | PIN_MODE_OUTPUT(GPIOB_LED) | \ |
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| 176 | PIN_MODE_ALTERNATE(GPIOB_BT_RTS) | \ |
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| 177 | PIN_MODE_ALTERNATE(GPIOB_BT_CTS) | \ |
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| 178 | PIN_MODE_OUTPUT(GPIOB_SYS_UART_UP)) |
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| 179 | #define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_POWER_EN) | \
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| 180 | PIN_OTYPE_OPENDRAIN(GPIOB_SYS_UART_DN) | \ |
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| 181 | PIN_OTYPE_PUSHPULL(GPIOB_BUZZER) | \ |
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| 182 | PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SCL2) | \ |
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| 183 | PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SDA2) | \ |
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| 184 | PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SCL1) | \ |
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| 185 | PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SDA1) | \ |
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| 186 | PIN_OTYPE_OPENDRAIN(GPIOB_LED) | \ |
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| 187 | PIN_OTYPE_PUSHPULL(GPIOB_BT_CTS) | \ |
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| 188 | PIN_OTYPE_OPENDRAIN(GPIOB_SYS_UART_UP)) |
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| 189 | #define VAL_GPIOB_OSPEEDR 0xFFFFFFFF |
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| 190 | #define VAL_GPIOB_PUPDR 0x00000000 |
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| 191 | #define VAL_GPIOB_ODR 0xFFFF |
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| 192 | #define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_BUZZER, 2)) |
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| 193 | #define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_GAUGE_SCL2, 4) | \ |
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| 194 | PIN_AFIO_AF(GPIOB_GAUGE_SDA2, 4) | \
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| 195 | PIN_AFIO_AF(GPIOB_GAUGE_SCL1, 4) | \
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| 196 | PIN_AFIO_AF(GPIOB_GAUGE_SDA1, 4) | \
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| 197 | PIN_AFIO_AF(GPIOB_BT_RTS, 7) | \
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| 198 | PIN_AFIO_AF(GPIOB_BT_CTS, 7))
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| 199 | |||
| 200 | /*
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| 201 | * Port C setup.
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| 202 | */
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| 203 | #define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_CHARGE_STAT1A) | \
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| 204 | PIN_MODE_INPUT(GPIOC_GAUGE_BATLOW1) | \ |
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| 205 | PIN_MODE_INPUT(GPIOC_GAUGE_BATGD1_N) | \ |
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| 206 | PIN_MODE_OUTPUT(GPIOC_CHARGE_EN1_N) | \ |
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| 207 | PIN_MODE_INPUT(GPIOC_IR_INT2_N) | \ |
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| 208 | PIN_MODE_INPUT(GPIOC_TOUCH_INT_N) | \ |
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| 209 | PIN_MODE_INPUT(GPIOC_SYS_DONE) | \ |
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| 210 | PIN_MODE_OUTPUT(GPIOC_SYS_PROG_N) | \ |
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| 211 | PIN_MODE_INPUT(GPIOC_PATH_DC) | \ |
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| 212 | PIN_MODE_OUTPUT(GPIOC_SYS_SPI_DIR) | \ |
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| 213 | PIN_MODE_ALTERNATE(GPIOC_BT_RX) | \ |
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| 214 | PIN_MODE_ALTERNATE(GPIOC_BT_TX) | \ |
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| 215 | PIN_MODE_OUTPUT(GPIOC_SYS_INT_N) | \ |
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| 216 | PIN_MODE_OUTPUT(GPIOC_SYS_PD_N) | \ |
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| 217 | PIN_MODE_OUTPUT(GPIOC_SYS_WARMRST_N) | \ |
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| 218 | PIN_MODE_OUTPUT(GPIOC_BT_RST)) |
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| 219 | #define VAL_GPIOC_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOC_CHARGE_EN1_N) | \
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| 220 | PIN_OTYPE_OPENDRAIN(GPIOC_SYS_PROG_N) | \ |
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| 221 | PIN_OTYPE_OPENDRAIN(GPIOC_SYS_SPI_DIR) | \ |
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| 222 | PIN_OTYPE_PUSHPULL(GPIOC_BT_RX) | \ |
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| 223 | PIN_OTYPE_OPENDRAIN(GPIOC_SYS_INT_N) | \ |
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| 224 | PIN_OTYPE_OPENDRAIN(GPIOC_SYS_PD_N) | \ |
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| 225 | PIN_OTYPE_OPENDRAIN(GPIOC_SYS_WARMRST_N) | \ |
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| 226 | PIN_OTYPE_OPENDRAIN(GPIOC_BT_RST)) |
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| 227 | #define VAL_GPIOC_OSPEEDR 0xFFFFFFFF |
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| 228 | #define VAL_GPIOC_PUPDR 0x00000000 |
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| 229 | #define VAL_GPIOC_ODR 0xEEFF /* emulate open drain for PATH_DC. This is required to prevent accidental shortcuts. Furthermore, pull down SYS_INT_N to indicate the OS is starting */ |
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| 230 | #define VAL_GPIOC_AFRL 0x00000000 |
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| 231 | #define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_BT_RX, 7) | \ |
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| 232 | PIN_AFIO_AF(GPIOC_BT_TX, 7))
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| 233 | |||
| 234 | /*
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| 235 | * Port D setup.
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| 236 | */
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| 237 | #define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \ |
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| 238 | PIN_MODE_INPUT(1) | \
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| 239 | PIN_MODE_OUTPUT(GPIOD_CHARGE_EN2_N) | \ |
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| 240 | PIN_MODE_INPUT(3) | \
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| 241 | PIN_MODE_INPUT(4) | \
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| 242 | PIN_MODE_INPUT(5) | \
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| 243 | PIN_MODE_INPUT(6) | \
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| 244 | PIN_MODE_INPUT(7) | \
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| 245 | PIN_MODE_INPUT(8) | \
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| 246 | PIN_MODE_INPUT(9) | \
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| 247 | PIN_MODE_INPUT(10) | \
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| 248 | PIN_MODE_INPUT(11) | \
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| 249 | PIN_MODE_INPUT(12) | \
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| 250 | PIN_MODE_INPUT(13) | \
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| 251 | PIN_MODE_INPUT(14) | \
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| 252 | PIN_MODE_INPUT(15))
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| 253 | #define VAL_GPIOD_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOD_CHARGE_EN2_N))
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| 254 | #define VAL_GPIOD_OSPEEDR 0xFFFFFFFF |
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| 255 | #define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \ |
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| 256 | PIN_PUDR_PULLUP(1) | \
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| 257 | PIN_PUDR_FLOATING(GPIOD_CHARGE_EN2_N) | \ |
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| 258 | PIN_PUDR_PULLUP(3) | \
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| 259 | PIN_PUDR_PULLUP(4) | \
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| 260 | PIN_PUDR_PULLUP(5) | \
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| 261 | PIN_PUDR_PULLUP(6) | \
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| 262 | PIN_PUDR_PULLUP(7) | \
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| 263 | PIN_PUDR_PULLUP(8) | \
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| 264 | PIN_PUDR_PULLUP(9) | \
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| 265 | PIN_PUDR_PULLUP(10) | \
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| 266 | PIN_PUDR_PULLUP(11) | \
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| 267 | PIN_PUDR_PULLUP(12) | \
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| 268 | PIN_PUDR_PULLUP(13) | \
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| 269 | PIN_PUDR_PULLUP(14) | \
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| 270 | PIN_PUDR_PULLUP(15))
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| 271 | #define VAL_GPIOD_ODR 0x0FFF |
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| 272 | #define VAL_GPIOD_AFRL 0x00000000 |
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| 273 | #define VAL_GPIOD_AFRH 0x00000000 |
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| 274 | |||
| 275 | /*
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| 276 | * Port E setup.
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| 277 | */
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| 278 | #define VAL_GPIOE_MODER 0x00000000 |
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| 279 | #define VAL_GPIOE_OTYPER 0x00000000 |
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| 280 | #define VAL_GPIOE_OSPEEDR 0xFFFFFFFF |
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| 281 | #define VAL_GPIOE_PUPDR 0xFFFFFFFF |
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| 282 | #define VAL_GPIOE_ODR 0xFFFF |
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| 283 | #define VAL_GPIOE_AFRL 0x00000000 |
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| 284 | #define VAL_GPIOE_AFRH 0x00000000 |
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| 285 | |||
| 286 | /*
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| 287 | * Port F setup.
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| 288 | * All input with pull-up.
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| 289 | */
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| 290 | #define VAL_GPIOF_MODER 0x00000000 |
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| 291 | #define VAL_GPIOF_OTYPER 0x00000000 |
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| 292 | #define VAL_GPIOF_OSPEEDR 0xFFFFFFFF |
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| 293 | #define VAL_GPIOF_PUPDR 0xFFFFFFFF |
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| 294 | #define VAL_GPIOF_ODR 0xFFFF |
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| 295 | #define VAL_GPIOF_AFRL 0x00000000 |
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| 296 | #define VAL_GPIOF_AFRH 0x00000000 |
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| 297 | |||
| 298 | /*
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| 299 | * Port G setup.
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| 300 | * All input with pull-up.
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| 301 | */
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| 302 | #define VAL_GPIOG_MODER 0x00000000 |
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| 303 | #define VAL_GPIOG_OTYPER 0x00000000 |
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| 304 | #define VAL_GPIOG_OSPEEDR 0xFFFFFFFF |
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| 305 | #define VAL_GPIOG_PUPDR 0xFFFFFFFF |
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| 306 | #define VAL_GPIOG_ODR 0xFFFF |
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| 307 | #define VAL_GPIOG_AFRL 0x00000000 |
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| 308 | #define VAL_GPIOG_AFRH 0x00000000 |
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| 309 | |||
| 310 | /*
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| 311 | * Port H setup.
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| 312 | */
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| 313 | #define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
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| 314 | PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ |
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| 315 | PIN_MODE_INPUT(2) | \
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| 316 | PIN_MODE_INPUT(3) | \
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| 317 | PIN_MODE_INPUT(4) | \
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| 318 | PIN_MODE_INPUT(5) | \
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| 319 | PIN_MODE_INPUT(6) | \
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| 320 | PIN_MODE_INPUT(7) | \
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| 321 | PIN_MODE_INPUT(8) | \
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| 322 | PIN_MODE_INPUT(9) | \
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| 323 | PIN_MODE_INPUT(10) | \
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| 324 | PIN_MODE_INPUT(11) | \
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| 325 | PIN_MODE_INPUT(12) | \
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| 326 | PIN_MODE_INPUT(13) | \
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| 327 | PIN_MODE_INPUT(14) | \
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| 328 | PIN_MODE_INPUT(15))
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| 329 | #define VAL_GPIOH_OTYPER 0x00000000 |
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| 330 | #define VAL_GPIOH_OSPEEDR 0xFFFFFFFF |
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| 331 | #define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
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| 332 | PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \ |
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| 333 | PIN_PUDR_PULLUP(2) | \
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| 334 | PIN_PUDR_PULLUP(3) | \
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| 335 | PIN_PUDR_PULLUP(4) | \
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| 336 | PIN_PUDR_PULLUP(5) | \
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| 337 | PIN_PUDR_PULLUP(6) | \
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| 338 | PIN_PUDR_PULLUP(7) | \
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| 339 | PIN_PUDR_PULLUP(8) | \
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| 340 | PIN_PUDR_PULLUP(9) | \
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| 341 | PIN_PUDR_PULLUP(10) | \
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| 342 | PIN_PUDR_PULLUP(11) | \
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| 343 | PIN_PUDR_PULLUP(12) | \
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| 344 | PIN_PUDR_PULLUP(13) | \
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| 345 | PIN_PUDR_PULLUP(14) | \
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| 346 | PIN_PUDR_PULLUP(15))
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| 347 | #define VAL_GPIOH_ODR 0xFFFF |
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| 348 | #define VAL_GPIOH_AFRL 0x00000000 |
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| 349 | #define VAL_GPIOH_AFRH 0x00000000 |
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| 350 | |||
| 351 | /*
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| 352 | * Port I setup.
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| 353 | * All input with pull-up.
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| 354 | */
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| 355 | #define VAL_GPIOI_MODER 0x00000000 |
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| 356 | #define VAL_GPIOI_OTYPER 0x00000000 |
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| 357 | #define VAL_GPIOI_OSPEEDR 0xFFFFFFFF |
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| 358 | #define VAL_GPIOI_PUPDR 0xFFFFFFFF |
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| 359 | #define VAL_GPIOI_ODR 0xFFFF |
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| 360 | #define VAL_GPIOI_AFRL 0x00000000 |
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| 361 | #define VAL_GPIOI_AFRH 0x00000000 |
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| 362 | |||
| 363 | #if !defined(_FROM_ASM_)
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| 364 | #ifdef __cplusplus
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| 365 | extern "C" { |
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| 366 | #endif
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| 367 | void boardInit(void); |
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| 368 | void boardWriteIoPower(int value); |
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| 369 | void boardWriteLed(int value); |
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| 370 | void boardWriteSystemPower(int value); |
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| 371 | void boardWriteWarmRestart(const uint8_t value); |
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| 372 | void boardChargerSetState(uint8_t chrg_mask, uint8_t state);
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| 373 | void boardBluetoothSetState(uint8_t state);
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| 374 | void boardRequestShutdown(void); |
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| 375 | void boardStandby(void); |
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| 376 | void boardStop(const uint8_t lpds, const uint8_t fpds); |
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| 377 | void boardWakeup(void); |
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| 378 | b4885314 | Thomas Schöpping | void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad); |
| 379 | void boardResetBQ27500I2C(const uint8_t scl_pad, const uint8_t sda_pad); |
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| 380 | 58fe0e0b | Thomas Schöpping | #ifdef __cplusplus
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| 381 | } |
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| 382 | #endif
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| 383 | #endif /* _FROM_ASM_ */ |
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| 384 | |||
| 385 | #endif /* _BOARD_H_ */ |