amiro-os / boards / DiWheelDrive / board.h @ bfffb0bd
History | View | Annotate | Download (7.952 KB)
1 | 58fe0e0b | Thomas Schöpping | #ifndef _BOARD_H_
|
---|---|---|---|
2 | #define _BOARD_H_
|
||
3 | |||
4 | /*
|
||
5 | * Setup for AMiRo DiWheelDrive board.
|
||
6 | */
|
||
7 | |||
8 | /*
|
||
9 | * Board identifier.
|
||
10 | */
|
||
11 | #define BOARD_DI_WHEEL_DRIVE
|
||
12 | #define BOARD_NAME "AMiRo DiWheelDrive" |
||
13 | #define BOARD_VERSION "1.1" |
||
14 | |||
15 | /*
|
||
16 | * Board frequencies.
|
||
17 | */
|
||
18 | #define STM32_LSECLK 0 |
||
19 | #define STM32_HSECLK 8000000 |
||
20 | |||
21 | /*
|
||
22 | * MCU type as defined in the ST header file stm32f1xx.h.
|
||
23 | */
|
||
24 | #define STM32F10X_HD
|
||
25 | |||
26 | /*
|
||
27 | * IO pins assignments.
|
||
28 | */
|
||
29 | #define GPIOA_WKUP 0 |
||
30 | #define GPIOA_LED 1 |
||
31 | #define GPIOA_DRIVE_PWM1A 2 |
||
32 | #define GPIOA_DRIVE_PWM1B 3 |
||
33 | #define GPIOA_MOTION_SCLK 5 |
||
34 | #define GPIOA_MOTION_MISO 6 |
||
35 | #define GPIOA_MOTION_MOSI 7 |
||
36 | #define GPIOA_PROG_RX 9 |
||
37 | #define GPIOA_PROG_TX 10 |
||
38 | #define GPIOA_CAN_RX 11 |
||
39 | #define GPIOA_CAN_TX 12 |
||
40 | #define GPIOA_SWDIO 13 |
||
41 | #define GPIOA_SWCLK 14 |
||
42 | #define GPIOA_DRIVE_PWM2B 15 |
||
43 | |||
44 | |||
45 | #define GPIOB_DRIVE_SENSE2 1 |
||
46 | #define GPIOB_POWER_EN 2 |
||
47 | #define GPIOB_DRIVE_PWM2A 3 |
||
48 | #define GPIOB_COMPASS_DRDY 5 |
||
49 | #define GPIOB_DRIVE_ENC1A 6 |
||
50 | #define GPIOB_DRIVE_ENC1B 7 |
||
51 | #define GPIOB_COMPASS_SCL 8 |
||
52 | #define GPIOB_COMPASS_SDA 9 |
||
53 | #define GPIOB_IR_SCL 10 |
||
54 | #define GPIOB_IR_SDA 11 |
||
55 | #define GPIOB_IR_INT 12 |
||
56 | #define GPIOB_GYRO_DRDY 13 |
||
57 | #define GPIOB_SYS_UART_UP 14 |
||
58 | #define GPIOB_ACCEL_INT_N 15 |
||
59 | |||
60 | #define GPIOC_DRIVE_SENSE1 0 |
||
61 | #define GPIOC_SYS_INT_N 1 |
||
62 | #define GPIOC_PATH_DCSTAT 3 |
||
63 | #define GPIOC_PATH_DCEN 5 |
||
64 | #define GPIOC_DRIVE_ENC2B 6 |
||
65 | #define GPIOC_DRIVE_ENC2A 7 |
||
66 | #define GPIOC_SYS_PD_N 8 |
||
67 | #define GPIOC_SYS_REG_EN 9 |
||
68 | #define GPIOC_SYS_UART_RX 10 |
||
69 | #define GPIOC_SYS_UART_TX 11 |
||
70 | #define GPIOC_ACCEL_SS_N 13 |
||
71 | #define GPIOC_GYRO_SS_N 14 |
||
72 | |||
73 | #define GPIOD_OSC_IN 0 |
||
74 | #define GPIOD_OSC_OUT 1 |
||
75 | #define GPIOD_SYS_WARMRST_N 2 |
||
76 | |||
77 | /*
|
||
78 | * I/O ports initial setup, this configuration is established soon after reset
|
||
79 | * in the initialization code.
|
||
80 | */
|
||
81 | #define PIN_MODE_INPUT(n) (0x4U << (((n) % 8) * 4)) |
||
82 | #define PIN_MODE_INPUT_PULLX(n) (0x8U << (((n) % 8) * 4)) |
||
83 | #define PIN_MODE_INPUT_ANALOG(n) (0x0U << (((n) % 8) * 4)) |
||
84 | /* Push Pull output 50MHz */
|
||
85 | #define PIN_MODE_OUTPUT_PUSHPULL(n) (0x3U << (((n) % 8) * 4)) |
||
86 | /* Open Drain output 50MHz */
|
||
87 | #define PIN_MODE_OUTPUT_OPENDRAIN(n) (0x7U << (((n) % 8) * 4)) |
||
88 | /* Alternate Push Pull output 50MHz */
|
||
89 | #define PIN_MODE_ALTERNATE_PUSHPULL(n) (0xbU << (((n) % 8) * 4)) |
||
90 | /* Alternate Open Drain output 50MHz */
|
||
91 | #define PIN_MODE_ALTERNATE_OPENDRAIN(n) (0xfU << (((n) % 8) * 4)) |
||
92 | |||
93 | /*
|
||
94 | * Port A setup.
|
||
95 | */
|
||
96 | #define VAL_GPIOACRL (PIN_MODE_INPUT(GPIOA_WKUP) | \
|
||
97 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOA_LED) | \ |
||
98 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1A) | \ |
||
99 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1B) | \ |
||
100 | PIN_MODE_INPUT_PULLX(4) | \
|
||
101 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_SCLK) | \ |
||
102 | PIN_MODE_INPUT_PULLX(GPIOA_MOTION_MISO) | \ |
||
103 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_MOSI)) |
||
104 | #define VAL_GPIOACRH (PIN_MODE_INPUT_PULLX(8) | \ |
||
105 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_PROG_RX) | \ |
||
106 | PIN_MODE_INPUT_PULLX(GPIOA_PROG_TX) | \ |
||
107 | PIN_MODE_INPUT_PULLX(GPIOA_CAN_RX) | \ |
||
108 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_CAN_TX) | \ |
||
109 | PIN_MODE_INPUT_PULLX(GPIOA_SWDIO) | \ |
||
110 | PIN_MODE_INPUT_PULLX(GPIOA_SWCLK) | \ |
||
111 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM2B)) |
||
112 | #define VAL_GPIOAODR 0xF7FF /* prevent power over CAN bug */ |
||
113 | |||
114 | /*
|
||
115 | * Port B setup.
|
||
116 | */
|
||
117 | #define VAL_GPIOBCRL (PIN_MODE_INPUT_PULLX(0) | \ |
||
118 | PIN_MODE_INPUT_ANALOG(GPIOB_DRIVE_SENSE2) | \ |
||
119 | PIN_MODE_OUTPUT_PUSHPULL(GPIOB_POWER_EN) | \ |
||
120 | PIN_MODE_ALTERNATE_PUSHPULL(GPIOB_DRIVE_PWM2A) | \ |
||
121 | PIN_MODE_INPUT_PULLX(4) | \
|
||
122 | PIN_MODE_INPUT_PULLX(GPIOB_COMPASS_DRDY) | \ |
||
123 | PIN_MODE_INPUT(GPIOB_DRIVE_ENC1A) | \ |
||
124 | PIN_MODE_INPUT(GPIOB_DRIVE_ENC1B)) |
||
125 | #define VAL_GPIOBCRH (PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SCL) | \
|
||
126 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SDA) | \ |
||
127 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SCL) | \ |
||
128 | PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SDA) | \ |
||
129 | PIN_MODE_INPUT(GPIOB_IR_INT) | \ |
||
130 | PIN_MODE_INPUT_PULLX(GPIOB_GYRO_DRDY) | \ |
||
131 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOB_SYS_UART_UP) | \ |
||
132 | PIN_MODE_INPUT_PULLX(GPIOB_ACCEL_INT_N)) |
||
133 | #define VAL_GPIOBODR 0xFFFB /* initially the motors are not powered */ |
||
134 | |||
135 | /*
|
||
136 | * Port C setup.
|
||
137 | */
|
||
138 | #define VAL_GPIOCCRL (PIN_MODE_INPUT_ANALOG(GPIOC_DRIVE_SENSE1) | \
|
||
139 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_INT_N) | \ |
||
140 | PIN_MODE_INPUT_PULLX(2) | \
|
||
141 | PIN_MODE_INPUT(GPIOC_PATH_DCSTAT) | \ |
||
142 | PIN_MODE_INPUT_PULLX(4) | \
|
||
143 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_PATH_DCEN) | \ |
||
144 | PIN_MODE_INPUT(GPIOC_DRIVE_ENC2B) | \ |
||
145 | PIN_MODE_INPUT(GPIOC_DRIVE_ENC2A)) |
||
146 | #define VAL_GPIOCCRH (PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_PD_N) | \
|
||
147 | PIN_MODE_INPUT(GPIOC_SYS_REG_EN) | \ |
||
148 | PIN_MODE_INPUT(GPIOC_SYS_UART_RX) | \ |
||
149 | PIN_MODE_INPUT(GPIOC_SYS_UART_TX) | \ |
||
150 | PIN_MODE_INPUT_PULLX(12) | \
|
||
151 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_ACCEL_SS_N) | \ |
||
152 | PIN_MODE_OUTPUT_PUSHPULL(GPIOC_GYRO_SS_N) | \ |
||
153 | PIN_MODE_INPUT_PULLX(15))
|
||
154 | #define VAL_GPIOCODR 0xFFDD /* initially charging via the pins is disabled and SYSNIN_N indicates that the OS is busy */ |
||
155 | |||
156 | /*
|
||
157 | * Port D setup.
|
||
158 | */
|
||
159 | #define VAL_GPIODCRL (PIN_MODE_INPUT(GPIOD_OSC_IN) | \
|
||
160 | PIN_MODE_INPUT(GPIOD_OSC_OUT) | \ |
||
161 | PIN_MODE_OUTPUT_OPENDRAIN(GPIOD_SYS_WARMRST_N) | \ |
||
162 | PIN_MODE_INPUT_PULLX(3) | \
|
||
163 | PIN_MODE_INPUT_PULLX(4) | \
|
||
164 | PIN_MODE_INPUT_PULLX(5) | \
|
||
165 | PIN_MODE_INPUT_PULLX(6) | \
|
||
166 | PIN_MODE_INPUT_PULLX(7))
|
||
167 | #define VAL_GPIODCRH 0x88888888 |
||
168 | #define VAL_GPIODODR 0xFFFF |
||
169 | |||
170 | /*
|
||
171 | * Port E setup.
|
||
172 | */
|
||
173 | #define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ |
||
174 | #define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ |
||
175 | #define VAL_GPIOEODR 0xFFFF |
||
176 | |||
177 | /*
|
||
178 | * Port F setup.
|
||
179 | */
|
||
180 | #define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ |
||
181 | #define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ |
||
182 | #define VAL_GPIOFODR 0xFFFF |
||
183 | |||
184 | /*
|
||
185 | * Port G setup.
|
||
186 | */
|
||
187 | #define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ |
||
188 | #define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ |
||
189 | #define VAL_GPIOGODR 0xFFFF |
||
190 | |||
191 | #if !defined(_FROM_ASM_)
|
||
192 | #ifdef __cplusplus
|
||
193 | extern "C" { |
||
194 | #endif
|
||
195 | void boardInit(void); |
||
196 | void boardWriteIoPower(const uint8_t value); |
||
197 | void boardWriteLed(int value); |
||
198 | void boardRequestShutdown(void); |
||
199 | void boardStandby(void); |
||
200 | void boardWakeup(void); |
||
201 | b4885314 | Thomas Schöpping | void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad); |
202 | 58fe0e0b | Thomas Schöpping | #ifdef __cplusplus
|
203 | } |
||
204 | #endif
|
||
205 | #endif /* _FROM_ASM_ */ |
||
206 | |||
207 | #endif /* _BOARD_H_ */ |