amiro-blt / Target / Modules / DiWheelDrive_1-2 / Boot / lib / CMSIS / CM3 / CoreSupport / core_cm3.c @ c1f21a71
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/**************************************************************************//** |
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* @file core_cm3.c
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
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* @version V1.30
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* @date 30. October 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h> |
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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#endif
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/* ################### Compiler specific Intrinsics ########################### */
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
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/* ARM armcc specific functions */
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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__ASM uint32_t __get_PSP(void)
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{ |
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mrs r0, psp |
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bx lr |
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} |
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|
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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__ASM void __set_PSP(uint32_t topOfProcStack)
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{ |
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msr psp, r0 |
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bx lr |
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} |
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/**
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* @brief Return the Main Stack Pointer
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*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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__ASM uint32_t __get_MSP(void)
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{ |
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mrs r0, msp |
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bx lr |
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} |
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|
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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__ASM void __set_MSP(uint32_t mainStackPointer)
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{ |
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msr msp, r0 |
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bx lr |
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} |
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|
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/**
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* @brief Reverse byte order in unsigned short value
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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__ASM uint32_t __REV16(uint16_t value) |
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{ |
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rev16 r0, r0 |
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bx lr |
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} |
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|
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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__ASM int32_t __REVSH(int16_t value) |
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{ |
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revsh r0, r0 |
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bx lr |
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} |
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#if (__ARMCC_VERSION < 400000) |
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/**
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* @brief Remove the exclusive lock created by ldrex
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*
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* Removes the exclusive lock which is created by ldrex.
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*/
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__ASM void __CLREX(void) |
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{ |
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clrex |
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} |
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|
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/**
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* @brief Return the Base Priority value
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*
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* @return BasePriority
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*
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* Return the content of the base priority register
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*/
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__ASM uint32_t __get_BASEPRI(void)
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{ |
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mrs r0, basepri |
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bx lr |
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} |
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|
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/**
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* @brief Set the Base Priority value
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*
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* @param basePri BasePriority
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*
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* Set the base priority register
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*/
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__ASM void __set_BASEPRI(uint32_t basePri)
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{ |
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msr basepri, r0 |
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bx lr |
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} |
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/**
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* @brief Return the Priority Mask value
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*
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* @return PriMask
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*
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* Return state of the priority mask bit from the priority mask register
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*/
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__ASM uint32_t __get_PRIMASK(void)
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{ |
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mrs r0, primask |
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bx lr |
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} |
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/**
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* @brief Set the Priority Mask value
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*
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* @param priMask PriMask
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*
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* Set the priority mask bit in the priority mask register
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*/
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__ASM void __set_PRIMASK(uint32_t priMask)
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{ |
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msr primask, r0 |
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bx lr |
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} |
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/**
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* @brief Return the Fault Mask value
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*
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* @return FaultMask
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*
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* Return the content of the fault mask register
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*/
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__ASM uint32_t __get_FAULTMASK(void)
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{ |
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mrs r0, faultmask |
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bx lr |
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} |
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/**
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* @brief Set the Fault Mask value
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*
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* @param faultMask faultMask value
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*
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* Set the fault mask register
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*/
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__ASM void __set_FAULTMASK(uint32_t faultMask)
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{ |
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msr faultmask, r0 |
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bx lr |
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} |
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/**
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* @brief Return the Control Register value
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*
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* @return Control value
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*
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* Return the content of the control register
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*/
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__ASM uint32_t __get_CONTROL(void)
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{ |
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mrs r0, control |
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bx lr |
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} |
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/**
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* @brief Set the Control Register value
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*
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* @param control Control value
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*
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* Set the control register
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*/
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__ASM void __set_CONTROL(uint32_t control)
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{ |
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msr control, r0 |
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bx lr |
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} |
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#endif /* __ARMCC_VERSION */ |
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#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
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/* IAR iccarm specific functions */
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#pragma diag_suppress=Pe940
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|
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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uint32_t __get_PSP(void)
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{ |
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__ASM("mrs r0, psp");
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__ASM("bx lr");
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} |
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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void __set_PSP(uint32_t topOfProcStack)
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{ |
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__ASM("msr psp, r0");
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__ASM("bx lr");
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} |
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/**
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* @brief Return the Main Stack Pointer
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*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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uint32_t __get_MSP(void)
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{ |
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__ASM("mrs r0, msp");
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__ASM("bx lr");
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} |
299 |
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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void __set_MSP(uint32_t topOfMainStack)
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{ |
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__ASM("msr msp, r0");
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__ASM("bx lr");
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} |
313 |
|
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/**
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* @brief Reverse byte order in unsigned short value
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316 |
*
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* @param value value to reverse
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318 |
* @return reversed value
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319 |
*
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* Reverse byte order in unsigned short value
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*/
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uint32_t __REV16(uint16_t value) |
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{ |
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__ASM("rev16 r0, r0");
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__ASM("bx lr");
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} |
327 |
|
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/**
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* @brief Reverse bit order of value
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse bit order of value
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*/
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uint32_t __RBIT(uint32_t value) |
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{ |
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__ASM("rbit r0, r0");
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__ASM("bx lr");
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} |
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/**
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* @brief LDR Exclusive (8 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 8 bit values)
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*/
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uint8_t __LDREXB(uint8_t *addr) |
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{ |
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__ASM("ldrexb r0, [r0]");
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__ASM("bx lr");
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} |
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|
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/**
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* @brief LDR Exclusive (16 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 16 bit values
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*/
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uint16_t __LDREXH(uint16_t *addr) |
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{ |
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__ASM("ldrexh r0, [r0]");
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__ASM("bx lr");
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} |
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|
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/**
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* @brief LDR Exclusive (32 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 32 bit values
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*/
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uint32_t __LDREXW(uint32_t *addr) |
379 |
{ |
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__ASM("ldrex r0, [r0]");
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__ASM("bx lr");
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} |
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|
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/**
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* @brief STR Exclusive (8 bit)
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*
|
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 8 bit values
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*/
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uint32_t __STREXB(uint8_t value, uint8_t *addr) |
394 |
{ |
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__ASM("strexb r0, r0, [r1]");
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__ASM("bx lr");
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} |
398 |
|
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/**
|
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* @brief STR Exclusive (16 bit)
|
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*
|
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* @param value value to store
|
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* @param *addr address pointer
|
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* @return successful / failed
|
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*
|
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* Exclusive STR command for 16 bit values
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*/
|
408 |
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
409 |
{ |
410 |
__ASM("strexh r0, r0, [r1]");
|
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__ASM("bx lr");
|
412 |
} |
413 |
|
414 |
/**
|
415 |
* @brief STR Exclusive (32 bit)
|
416 |
*
|
417 |
* @param value value to store
|
418 |
* @param *addr address pointer
|
419 |
* @return successful / failed
|
420 |
*
|
421 |
* Exclusive STR command for 32 bit values
|
422 |
*/
|
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uint32_t __STREXW(uint32_t value, uint32_t *addr) |
424 |
{ |
425 |
__ASM("strex r0, r0, [r1]");
|
426 |
__ASM("bx lr");
|
427 |
} |
428 |
|
429 |
#pragma diag_default=Pe940
|
430 |
|
431 |
|
432 |
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
433 |
/* GNU gcc specific functions */
|
434 |
|
435 |
/**
|
436 |
* @brief Return the Process Stack Pointer
|
437 |
*
|
438 |
* @return ProcessStackPointer
|
439 |
*
|
440 |
* Return the actual process stack pointer
|
441 |
*/
|
442 |
uint32_t __get_PSP(void) __attribute__( ( naked ) );
|
443 |
uint32_t __get_PSP(void)
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444 |
{ |
445 |
uint32_t result=0;
|
446 |
|
447 |
__ASM volatile ("MRS %0, psp\n\t" |
448 |
"MOV r0, %0 \n\t"
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449 |
"BX lr \n\t" : "=r" (result) ); |
450 |
return(result);
|
451 |
} |
452 |
|
453 |
/**
|
454 |
* @brief Set the Process Stack Pointer
|
455 |
*
|
456 |
* @param topOfProcStack Process Stack Pointer
|
457 |
*
|
458 |
* Assign the value ProcessStackPointer to the MSP
|
459 |
* (process stack pointer) Cortex processor register
|
460 |
*/
|
461 |
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
|
462 |
void __set_PSP(uint32_t topOfProcStack)
|
463 |
{ |
464 |
__ASM volatile ("MSR psp, %0\n\t" |
465 |
"BX lr \n\t" : : "r" (topOfProcStack) ); |
466 |
} |
467 |
|
468 |
/**
|
469 |
* @brief Return the Main Stack Pointer
|
470 |
*
|
471 |
* @return Main Stack Pointer
|
472 |
*
|
473 |
* Return the current value of the MSP (main stack pointer)
|
474 |
* Cortex processor register
|
475 |
*/
|
476 |
uint32_t __get_MSP(void) __attribute__( ( naked ) );
|
477 |
uint32_t __get_MSP(void)
|
478 |
{ |
479 |
uint32_t result=0;
|
480 |
|
481 |
__ASM volatile ("MRS %0, msp\n\t" |
482 |
"MOV r0, %0 \n\t"
|
483 |
"BX lr \n\t" : "=r" (result) ); |
484 |
return(result);
|
485 |
} |
486 |
|
487 |
/**
|
488 |
* @brief Set the Main Stack Pointer
|
489 |
*
|
490 |
* @param topOfMainStack Main Stack Pointer
|
491 |
*
|
492 |
* Assign the value mainStackPointer to the MSP
|
493 |
* (main stack pointer) Cortex processor register
|
494 |
*/
|
495 |
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
|
496 |
void __set_MSP(uint32_t topOfMainStack)
|
497 |
{ |
498 |
__ASM volatile ("MSR msp, %0\n\t" |
499 |
"BX lr \n\t" : : "r" (topOfMainStack) ); |
500 |
} |
501 |
|
502 |
/**
|
503 |
* @brief Return the Base Priority value
|
504 |
*
|
505 |
* @return BasePriority
|
506 |
*
|
507 |
* Return the content of the base priority register
|
508 |
*/
|
509 |
uint32_t __get_BASEPRI(void)
|
510 |
{ |
511 |
uint32_t result=0;
|
512 |
|
513 |
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
514 |
return(result);
|
515 |
} |
516 |
|
517 |
/**
|
518 |
* @brief Set the Base Priority value
|
519 |
*
|
520 |
* @param basePri BasePriority
|
521 |
*
|
522 |
* Set the base priority register
|
523 |
*/
|
524 |
void __set_BASEPRI(uint32_t value)
|
525 |
{ |
526 |
__ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
527 |
} |
528 |
|
529 |
/**
|
530 |
* @brief Return the Priority Mask value
|
531 |
*
|
532 |
* @return PriMask
|
533 |
*
|
534 |
* Return state of the priority mask bit from the priority mask register
|
535 |
*/
|
536 |
uint32_t __get_PRIMASK(void)
|
537 |
{ |
538 |
uint32_t result=0;
|
539 |
|
540 |
__ASM volatile ("MRS %0, primask" : "=r" (result) ); |
541 |
return(result);
|
542 |
} |
543 |
|
544 |
/**
|
545 |
* @brief Set the Priority Mask value
|
546 |
*
|
547 |
* @param priMask PriMask
|
548 |
*
|
549 |
* Set the priority mask bit in the priority mask register
|
550 |
*/
|
551 |
void __set_PRIMASK(uint32_t priMask)
|
552 |
{ |
553 |
__ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
554 |
} |
555 |
|
556 |
/**
|
557 |
* @brief Return the Fault Mask value
|
558 |
*
|
559 |
* @return FaultMask
|
560 |
*
|
561 |
* Return the content of the fault mask register
|
562 |
*/
|
563 |
uint32_t __get_FAULTMASK(void)
|
564 |
{ |
565 |
uint32_t result=0;
|
566 |
|
567 |
__ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
568 |
return(result);
|
569 |
} |
570 |
|
571 |
/**
|
572 |
* @brief Set the Fault Mask value
|
573 |
*
|
574 |
* @param faultMask faultMask value
|
575 |
*
|
576 |
* Set the fault mask register
|
577 |
*/
|
578 |
void __set_FAULTMASK(uint32_t faultMask)
|
579 |
{ |
580 |
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
581 |
} |
582 |
|
583 |
/**
|
584 |
* @brief Return the Control Register value
|
585 |
*
|
586 |
* @return Control value
|
587 |
*
|
588 |
* Return the content of the control register
|
589 |
*/
|
590 |
uint32_t __get_CONTROL(void)
|
591 |
{ |
592 |
uint32_t result=0;
|
593 |
|
594 |
__ASM volatile ("MRS %0, control" : "=r" (result) ); |
595 |
return(result);
|
596 |
} |
597 |
|
598 |
/**
|
599 |
* @brief Set the Control Register value
|
600 |
*
|
601 |
* @param control Control value
|
602 |
*
|
603 |
* Set the control register
|
604 |
*/
|
605 |
void __set_CONTROL(uint32_t control)
|
606 |
{ |
607 |
__ASM volatile ("MSR control, %0" : : "r" (control) ); |
608 |
} |
609 |
|
610 |
|
611 |
/**
|
612 |
* @brief Reverse byte order in integer value
|
613 |
*
|
614 |
* @param value value to reverse
|
615 |
* @return reversed value
|
616 |
*
|
617 |
* Reverse byte order in integer value
|
618 |
*/
|
619 |
uint32_t __REV(uint32_t value) |
620 |
{ |
621 |
uint32_t result=0;
|
622 |
|
623 |
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
624 |
return(result);
|
625 |
} |
626 |
|
627 |
/**
|
628 |
* @brief Reverse byte order in unsigned short value
|
629 |
*
|
630 |
* @param value value to reverse
|
631 |
* @return reversed value
|
632 |
*
|
633 |
* Reverse byte order in unsigned short value
|
634 |
*/
|
635 |
uint32_t __REV16(uint16_t value) |
636 |
{ |
637 |
uint32_t result=0;
|
638 |
|
639 |
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
640 |
return(result);
|
641 |
} |
642 |
|
643 |
/**
|
644 |
* @brief Reverse byte order in signed short value with sign extension to integer
|
645 |
*
|
646 |
* @param value value to reverse
|
647 |
* @return reversed value
|
648 |
*
|
649 |
* Reverse byte order in signed short value with sign extension to integer
|
650 |
*/
|
651 |
int32_t __REVSH(int16_t value) |
652 |
{ |
653 |
uint32_t result=0;
|
654 |
|
655 |
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
656 |
return(result);
|
657 |
} |
658 |
|
659 |
/**
|
660 |
* @brief Reverse bit order of value
|
661 |
*
|
662 |
* @param value value to reverse
|
663 |
* @return reversed value
|
664 |
*
|
665 |
* Reverse bit order of value
|
666 |
*/
|
667 |
uint32_t __RBIT(uint32_t value) |
668 |
{ |
669 |
uint32_t result=0;
|
670 |
|
671 |
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
672 |
return(result);
|
673 |
} |
674 |
|
675 |
/**
|
676 |
* @brief LDR Exclusive (8 bit)
|
677 |
*
|
678 |
* @param *addr address pointer
|
679 |
* @return value of (*address)
|
680 |
*
|
681 |
* Exclusive LDR command for 8 bit value
|
682 |
*/
|
683 |
uint8_t __LDREXB(uint8_t *addr) |
684 |
{ |
685 |
uint8_t result=0;
|
686 |
|
687 |
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
688 |
return(result);
|
689 |
} |
690 |
|
691 |
/**
|
692 |
* @brief LDR Exclusive (16 bit)
|
693 |
*
|
694 |
* @param *addr address pointer
|
695 |
* @return value of (*address)
|
696 |
*
|
697 |
* Exclusive LDR command for 16 bit values
|
698 |
*/
|
699 |
uint16_t __LDREXH(uint16_t *addr) |
700 |
{ |
701 |
uint16_t result=0;
|
702 |
|
703 |
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
704 |
return(result);
|
705 |
} |
706 |
|
707 |
/**
|
708 |
* @brief LDR Exclusive (32 bit)
|
709 |
*
|
710 |
* @param *addr address pointer
|
711 |
* @return value of (*address)
|
712 |
*
|
713 |
* Exclusive LDR command for 32 bit values
|
714 |
*/
|
715 |
uint32_t __LDREXW(uint32_t *addr) |
716 |
{ |
717 |
uint32_t result=0;
|
718 |
|
719 |
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
720 |
return(result);
|
721 |
} |
722 |
|
723 |
/**
|
724 |
* @brief STR Exclusive (8 bit)
|
725 |
*
|
726 |
* @param value value to store
|
727 |
* @param *addr address pointer
|
728 |
* @return successful / failed
|
729 |
*
|
730 |
* Exclusive STR command for 8 bit values
|
731 |
*/
|
732 |
uint32_t __STREXB(uint8_t value, uint8_t *addr) |
733 |
{ |
734 |
uint32_t result=0;
|
735 |
|
736 |
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
737 |
return(result);
|
738 |
} |
739 |
|
740 |
/**
|
741 |
* @brief STR Exclusive (16 bit)
|
742 |
*
|
743 |
* @param value value to store
|
744 |
* @param *addr address pointer
|
745 |
* @return successful / failed
|
746 |
*
|
747 |
* Exclusive STR command for 16 bit values
|
748 |
*/
|
749 |
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
750 |
{ |
751 |
uint32_t result=0;
|
752 |
|
753 |
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
754 |
return(result);
|
755 |
} |
756 |
|
757 |
/**
|
758 |
* @brief STR Exclusive (32 bit)
|
759 |
*
|
760 |
* @param value value to store
|
761 |
* @param *addr address pointer
|
762 |
* @return successful / failed
|
763 |
*
|
764 |
* Exclusive STR command for 32 bit values
|
765 |
*/
|
766 |
uint32_t __STREXW(uint32_t value, uint32_t *addr) |
767 |
{ |
768 |
uint32_t result=0;
|
769 |
|
770 |
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
771 |
return(result);
|
772 |
} |
773 |
|
774 |
|
775 |
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
776 |
/* TASKING carm specific functions */
|
777 |
|
778 |
/*
|
779 |
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
780 |
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
781 |
* Including the CMSIS ones.
|
782 |
*/
|
783 |
|
784 |
#endif
|