amiro-os / modules / DiWheelDrive_1-1 / board.h @ 07ff44a7
History | View | Annotate | Download (41.4 KB)
1 | e545e620 | Thomas Schöpping | /*
|
---|---|---|---|
2 | AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
|
||
3 | Copyright (C) 2016..2018 Thomas Schöpping et al.
|
||
4 | |||
5 | This program is free software: you can redistribute it and/or modify
|
||
6 | it under the terms of the GNU General Public License as published by
|
||
7 | the Free Software Foundation, either version 3 of the License, or
|
||
8 | (at your option) any later version.
|
||
9 | |||
10 | This program is distributed in the hope that it will be useful,
|
||
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
13 | GNU General Public License for more details.
|
||
14 | |||
15 | You should have received a copy of the GNU General Public License
|
||
16 | along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||
17 | */
|
||
18 | |||
19 | 53710ca3 | Marc Rothmann | /**
|
20 | 37bacabf | Thomas Schöpping | * @file
|
21 | 53710ca3 | Marc Rothmann | * @brief DiWheeDrive v1.1 Board specific macros.
|
22 | *
|
||
23 | * @addtogroup diwheeldrive_board
|
||
24 | * @{
|
||
25 | */
|
||
26 | |||
27 | e545e620 | Thomas Schöpping | #ifndef _BOARD_H_
|
28 | #define _BOARD_H_
|
||
29 | |||
30 | /*
|
||
31 | 043cdf33 | Thomas Schöpping | * Setup for AMiRo DiWheelDrive v1.1 board.
|
32 | e545e620 | Thomas Schöpping | */
|
33 | |||
34 | /*
|
||
35 | * Board identifier.
|
||
36 | */
|
||
37 | #define BOARD_DIWHEELDRIVE
|
||
38 | #define BOARD_NAME "AMiRo DiWheelDrive" |
||
39 | #define BOARD_VERSION "1.1" |
||
40 | |||
41 | /*
|
||
42 | * Board oscillators-related settings.
|
||
43 | * NOTE: LSE not fitted.
|
||
44 | */
|
||
45 | #if !defined(STM32_LSECLK)
|
||
46 | #define STM32_LSECLK 0U |
||
47 | #endif
|
||
48 | |||
49 | #if !defined(STM32_HSECLK)
|
||
50 | #define STM32_HSECLK 8000000U |
||
51 | #endif
|
||
52 | |||
53 | /*
|
||
54 | * Board voltages.
|
||
55 | * Required for performance limits calculation.
|
||
56 | */
|
||
57 | #define STM32_VDD 330U |
||
58 | |||
59 | /*
|
||
60 | * MCU type as defined in the ST header.
|
||
61 | */
|
||
62 | #define STM32F103xE
|
||
63 | |||
64 | /*
|
||
65 | * IO pins assignments.
|
||
66 | */
|
||
67 | #define GPIOA_WKUP 0U |
||
68 | #define GPIOA_LED 1U |
||
69 | #define GPIOA_DRIVE_PWM1A 2U |
||
70 | #define GPIOA_DRIVE_PWM1B 3U |
||
71 | #define GPIOA_PIN4 4U |
||
72 | #define GPIOA_MOTION_SCLK 5U |
||
73 | #define GPIOA_MOTION_MISO 6U |
||
74 | #define GPIOA_MOTION_MOSI 7U |
||
75 | #define GPIOA_PIN8 8U |
||
76 | #define GPIOA_PROG_RX 9U |
||
77 | #define GPIOA_PROG_TX 10U |
||
78 | #define GPIOA_CAN_RX 11U |
||
79 | #define GPIOA_CAN_TX 12U |
||
80 | #define GPIOA_SWDIO 13U |
||
81 | #define GPIOA_SWCLK 14U |
||
82 | #define GPIOA_DRIVE_PWM2B 15U |
||
83 | |||
84 | #define GPIOB_PIN0 0U |
||
85 | #define GPIOB_DRIVE_SENSE2 1U |
||
86 | #define GPIOB_POWER_EN 2U |
||
87 | #define GPIOB_DRIVE_PWM2A 3U |
||
88 | #define GPIOB_PIN4 4U |
||
89 | #define GPIOB_COMPASS_DRDY 5U |
||
90 | #define GPIOB_DRIVE_ENC1A 6U |
||
91 | #define GPIOB_DRIVE_ENC1B 7U |
||
92 | #define GPIOB_COMPASS_SCL 8U |
||
93 | #define GPIOB_COMPASS_SDA 9U |
||
94 | #define GPIOB_IR_SCL 10U |
||
95 | #define GPIOB_IR_SDA 11U |
||
96 | #define GPIOB_IR_INT 12U |
||
97 | #define GPIOB_GYRO_DRDY 13U |
||
98 | #define GPIOB_SYS_UART_UP 14U |
||
99 | #define GPIOB_ACCEL_INT_N 15U |
||
100 | |||
101 | #define GPIOC_DRIVE_SENSE1 0U |
||
102 | #define GPIOC_SYS_INT_N 1U |
||
103 | #define GPIOC_PIN2 2U |
||
104 | #define GPIOC_PATH_DCSTAT 3U |
||
105 | #define GPIOC_PIN4 4U |
||
106 | #define GPIOC_PATH_DCEN 5U |
||
107 | #define GPIOC_DRIVE_ENC2B 6U |
||
108 | #define GPIOC_DRIVE_ENC2A 7U |
||
109 | #define GPIOC_SYS_PD_N 8U |
||
110 | #define GPIOC_SYS_REG_EN 9U |
||
111 | #define GPIOC_SYS_UART_RX 10U |
||
112 | #define GPIOC_SYS_UART_TX 11U |
||
113 | #define GPIOC_PIN12 12U |
||
114 | #define GPIOC_ACCEL_SS_N 13U |
||
115 | #define GPIOC_GYRO_SS_N 14U |
||
116 | #define GPIOC_PIN15 15U |
||
117 | |||
118 | #define GPIOD_OSC_IN 0U |
||
119 | #define GPIOD_OSC_OUT 1U |
||
120 | #define GPIOD_SYS_WARMRST_N 2U |
||
121 | #define GPIOD_PIN3 3U |
||
122 | #define GPIOD_PIN4 4U |
||
123 | #define GPIOD_PIN5 5U |
||
124 | #define GPIOD_PIN6 6U |
||
125 | #define GPIOD_PIN7 7U |
||
126 | #define GPIOD_PIN8 8U |
||
127 | #define GPIOD_PIN9 9U |
||
128 | #define GPIOD_PIN10 10U |
||
129 | #define GPIOD_PIN11 11U |
||
130 | #define GPIOD_PIN12 12U |
||
131 | #define GPIOD_PIN13 13U |
||
132 | #define GPIOD_PIN14 14U |
||
133 | #define GPIOD_PIN15 15U |
||
134 | |||
135 | #define GPIOE_PIN0 0U |
||
136 | #define GPIOE_PIN1 1U |
||
137 | #define GPIOE_PIN2 2U |
||
138 | #define GPIOE_PIN3 3U |
||
139 | #define GPIOE_PIN4 4U |
||
140 | #define GPIOE_PIN5 5U |
||
141 | #define GPIOE_PIN6 6U |
||
142 | #define GPIOE_PIN7 7U |
||
143 | #define GPIOE_PIN8 8U |
||
144 | #define GPIOE_PIN9 9U |
||
145 | #define GPIOE_PIN10 10U |
||
146 | #define GPIOE_PIN11 11U |
||
147 | #define GPIOE_PIN12 12U |
||
148 | #define GPIOE_PIN13 13U |
||
149 | #define GPIOE_PIN14 14U |
||
150 | #define GPIOE_PIN15 15U |
||
151 | |||
152 | #define GPIOF_PIN0 0U |
||
153 | #define GPIOF_PIN1 1U |
||
154 | #define GPIOF_PIN2 2U |
||
155 | #define GPIOF_PIN3 3U |
||
156 | #define GPIOF_PIN4 4U |
||
157 | #define GPIOF_PIN5 5U |
||
158 | #define GPIOF_PIN6 6U |
||
159 | #define GPIOF_PIN7 7U |
||
160 | #define GPIOF_PIN8 8U |
||
161 | #define GPIOF_PIN9 9U |
||
162 | #define GPIOF_PIN10 10U |
||
163 | #define GPIOF_PIN11 11U |
||
164 | #define GPIOF_PIN12 12U |
||
165 | #define GPIOF_PIN13 13U |
||
166 | #define GPIOF_PIN14 14U |
||
167 | #define GPIOF_PIN15 15U |
||
168 | |||
169 | #define GPIOG_PIN0 0U |
||
170 | #define GPIOG_PIN1 1U |
||
171 | #define GPIOG_PIN2 2U |
||
172 | #define GPIOG_PIN3 3U |
||
173 | #define GPIOG_PIN4 4U |
||
174 | #define GPIOG_PIN5 5U |
||
175 | #define GPIOG_PIN6 6U |
||
176 | #define GPIOG_PIN7 7U |
||
177 | #define GPIOG_PIN8 8U |
||
178 | #define GPIOG_PIN9 9U |
||
179 | #define GPIOG_PIN10 10U |
||
180 | #define GPIOG_PIN11 11U |
||
181 | #define GPIOG_PIN12 12U |
||
182 | #define GPIOG_PIN13 13U |
||
183 | #define GPIOG_PIN14 14U |
||
184 | #define GPIOG_PIN15 15U |
||
185 | |||
186 | /*
|
||
187 | * IO lines assignments.
|
||
188 | */
|
||
189 | #define LINE_WKUP PAL_LINE(GPIOA, GPIOA_WKUP)
|
||
190 | #define LINE_LED PAL_LINE(GPIOA, GPIOA_LED)
|
||
191 | #define LINE_DRIVE_PWM1A PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A)
|
||
192 | #define LINE_DRIVE_PWM1B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B)
|
||
193 | #define LINE_MOTION_SCLK PAL_LINE(GPIOA, GPIOA_MOTION_SCLK)
|
||
194 | #define LINE_MOTION_MISO PAL_LINE(GPIOA, GPIOA_MOTION_MISO)
|
||
195 | #define LINE_MOTION_MOSI PAL_LINE(GPIOA, GPIOA_MOTION_MOSI)
|
||
196 | #define LINE_PROG_RX PAL_LINE(GPIOA, GPIOA_PROG_RX)
|
||
197 | #define LINE_PROG_TX PAL_LINE(GPIOA, GPIOA_PROG_TX)
|
||
198 | #define LINE_CAN_RX PAL_LINE(GPIOA, GPIOA_CAN_RX)
|
||
199 | #define LINE_CAN_TX PAL_LINE(GPIOA, GPIOA_CAN_TX)
|
||
200 | #define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO)
|
||
201 | #define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK)
|
||
202 | #define LINE_DRIVE_PWM2B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B)
|
||
203 | |||
204 | #define LINE_DRIVE_SENSE2 PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2)
|
||
205 | #define LINE_POWER_EN PAL_LINE(GPIOB, GPIOB_POWER_EN)
|
||
206 | #define LINE_DRIVE_PWM2A PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A)
|
||
207 | #define LINE_COMPASS_DRDY PAL_LINE(GPIOB, GPIOB_COMPASS_DRDY)
|
||
208 | #define LINE_DRIVE_ENC1A PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A)
|
||
209 | #define LINE_DRIVE_ENC1B PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B)
|
||
210 | #define LINE_COMPASS_SCL PAL_LINE(GPIOB, GPIOB_COMPASS_SCL)
|
||
211 | #define LINE_COMPASS_SDA PAL_LINE(GPIOB, GPIOB_COMPASS_SDA)
|
||
212 | #define LINE_IR_SCL PAL_LINE(GPIOB, GPIOB_IR_SCL)
|
||
213 | #define LINE_IR_SDA PAL_LINE(GPIOB, GPIOB_IR_SDA)
|
||
214 | #define LINE_IR_INT PAL_LINE(GPIOB, GPIOB_IR_INT)
|
||
215 | #define LINE_GYRO_DRDY PAL_LINE(GPIOB, GPIOB_GYRO_DRDY)
|
||
216 | #define LINE_SYS_UART_UP PAL_LINE(GPIOB, GPIOB_SYS_UART_UP)
|
||
217 | #define LINE_ACCEL_INT_N PAL_LINE(GPIOB, GPIOB_ACCEL_INT_N)
|
||
218 | |||
219 | #define LINE_DRIVE_SENSE1 PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1)
|
||
220 | #define LINE_SYS_INT_N PAL_LINE(GPIOC, GPIOC_SYS_INT_N)
|
||
221 | #define LINE_PATH_DCSTAT PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT)
|
||
222 | #define LINE_PATH_DCEN PAL_LINE(GPIOC, GPIOC_PATH_DCEN)
|
||
223 | #define LINE_DRIVE_ENC2B PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B)
|
||
224 | #define LINE_DRIVE_ENC2A PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A)
|
||
225 | #define LINE_SYS_PD_N PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
|
||
226 | #define LINE_SYS_REG_EN PAL_LINE(GPIOC, GPIOC_SYS_REG_EN)
|
||
227 | #define LINE_SYS_UART_RX PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
|
||
228 | #define LINE_SYS_UART_TX PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
|
||
229 | #define LINE_ACCEL_SS_N PAL_LINE(GPIOC, GPIOC_ACCEL_SS_N)
|
||
230 | #define LINE_GYRO_SS_N PAL_LINE(GPIOC, GPIOC_GYRO_SS_N)
|
||
231 | |||
232 | #define LINE_OSC_IN PAL_LINE(GPIOD, GPIOD_OSC_IN)
|
||
233 | #define LINE_OSC_OUT PAL_LINE(GPIOD, GPIOD_OSC_OUT)
|
||
234 | #define LINE_SYS_WARMRST_N PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N)
|
||
235 | |||
236 | /*
|
||
237 | * I/O ports initial setup, this configuration is established soon after reset
|
||
238 | * in the initialization code.
|
||
239 | * Please refer to the STM32 Reference Manual for details.
|
||
240 | */
|
||
241 | #define PIN_MODE_INPUT 0U |
||
242 | #define PIN_MODE_OUTPUT_2M 2U |
||
243 | #define PIN_MODE_OUTPUT_10M 1U |
||
244 | #define PIN_MODE_OUTPUT_50M 3U |
||
245 | #define PIN_CNF_INPUT_ANALOG 0U |
||
246 | #define PIN_CNF_INPUT_FLOATING 1U |
||
247 | #define PIN_CNF_INPUT_PULLX 2U |
||
248 | #define PIN_CNF_OUTPUT_PUSHPULL 0U |
||
249 | #define PIN_CNF_OUTPUT_OPENDRAIN 1U |
||
250 | #define PIN_CNF_ALTERNATE_PUSHPULL 2U |
||
251 | #define PIN_CNF_ALTERNATE_OPENDRAIN 3U |
||
252 | #define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
||
253 | #define PIN_ODR_LOW(n) (0U << (n)) |
||
254 | #define PIN_ODR_HIGH(n) (1U << (n)) |
||
255 | 37bacabf | Thomas Schöpping | #define PIN_IGNORE(n) (1U << (n)) |
256 | e545e620 | Thomas Schöpping | |
257 | /*
|
||
258 | * GPIOA setup:
|
||
259 | *
|
||
260 | * PA0 - WKUP (input floating)
|
||
261 | * PA1 - LED (output opendrain high 50MHz)
|
||
262 | * PA2 - DRIVE_PWM1A (alternate pushpull 50MHz)
|
||
263 | * PA3 - DRIVE_PWM1B (alternate pushpull 50MHz)
|
||
264 | * PA4 - PIN4 (input floating)
|
||
265 | * PA5 - MOTION_SCLK (alternate pushpull 50MHz)
|
||
266 | * PA6 - MOTION_MISO (input pullup)
|
||
267 | * PA7 - MOTION_MOSI (alternate pushpull 50MHz)
|
||
268 | * PA8 - PIN8 (input floating)
|
||
269 | * PA9 - PROG_RX (alternate pushpull 50MHz)
|
||
270 | * PA10 - PROG_TX (input pullup)
|
||
271 | * PA11 - CAN_RX (input pullup)
|
||
272 | 933df08e | Thomas Schöpping | * PA12 - CAN_TX (alternate pushpull 50MHz)
|
273 | e545e620 | Thomas Schöpping | * PA13 - SWDIO (input pullup)
|
274 | * PA14 - SWCLK (input pullup)
|
||
275 | * PA15 - DRIVE_PWM2B (alternate pushpull 50MHz)
|
||
276 | */
|
||
277 | 37bacabf | Thomas Schöpping | #define VAL_GPIOAIGN (PIN_IGNORE(GPIOA_LED)) & 0 |
278 | e545e620 | Thomas Schöpping | #define VAL_GPIOACRL (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
279 | PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
||
280 | PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
||
281 | PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
||
282 | PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
283 | PIN_CR(GPIOA_MOTION_SCLK, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
||
284 | PIN_CR(GPIOA_MOTION_MISO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
285 | PIN_CR(GPIOA_MOTION_MOSI, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
||
286 | #define VAL_GPIOACRH (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
||
287 | PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
||
288 | PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
289 | PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
290 | 933df08e | Thomas Schöpping | PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
291 | e545e620 | Thomas Schöpping | PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
292 | PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
293 | PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
||
294 | #define VAL_GPIOAODR (PIN_ODR_HIGH(GPIOA_WKUP) | \
|
||
295 | PIN_ODR_HIGH(GPIOA_LED) | \ |
||
296 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) | \ |
||
297 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) | \ |
||
298 | PIN_ODR_LOW(GPIOA_PIN4) | \ |
||
299 | PIN_ODR_HIGH(GPIOA_MOTION_SCLK) | \ |
||
300 | PIN_ODR_HIGH(GPIOA_MOTION_MISO) | \ |
||
301 | PIN_ODR_HIGH(GPIOA_MOTION_MOSI) | \ |
||
302 | PIN_ODR_LOW(GPIOA_PIN8) | \ |
||
303 | PIN_ODR_HIGH(GPIOA_PROG_RX) | \ |
||
304 | PIN_ODR_HIGH(GPIOA_PROG_TX) | \ |
||
305 | PIN_ODR_HIGH(GPIOA_CAN_RX) | \ |
||
306 | PIN_ODR_HIGH(GPIOA_CAN_TX) | \ |
||
307 | PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
||
308 | PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
||
309 | PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B)) |
||
310 | |||
311 | /*
|
||
312 | * GPIOB setup:
|
||
313 | *
|
||
314 | * PB0 - PIN0 (input floating)
|
||
315 | * PB1 - DRIVE_SENSE2 (input analog)
|
||
316 | * PB2 - POWER_EN (output pushpull low 50MHz)
|
||
317 | * PB3 - DRIVE_PWM2A (alternate pushpull 50MHz)
|
||
318 | * PB4 - PIN4 (input floating)
|
||
319 | * PB5 - COMPASS_DRDY (input pullup)
|
||
320 | * PB6 - DRIVE_ENC1A (input floating)
|
||
321 | * PB7 - DRIVE_ENC1B (input floating)
|
||
322 | * PB8 - COMPASS_SCL (alternate opendrain 50MHz)
|
||
323 | * PB9 - COMPASS_SDA (alternate opendrain 50MHz)
|
||
324 | * PB10 - IR_SCL (alternate opendrain 50MHz)
|
||
325 | * PB11 - IR_SDA (alternate opendrain 50MHz)
|
||
326 | * PB12 - IR_INT (input pullup)
|
||
327 | * PB13 - GYRO_DRDY (input pullup)
|
||
328 | * PB14 - SYS_UART_UP (output opendrain high 50MHz)
|
||
329 | * PB15 - ACCEL_INT_N (input pullup)
|
||
330 | */
|
||
331 | 37bacabf | Thomas Schöpping | #define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
332 | e545e620 | Thomas Schöpping | #define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
333 | PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
||
334 | PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
||
335 | PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
||
336 | PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
337 | PIN_CR(GPIOB_COMPASS_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
338 | PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
339 | PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
340 | #define VAL_GPIOBCRH (PIN_CR(GPIOB_COMPASS_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \
|
||
341 | PIN_CR(GPIOB_COMPASS_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
||
342 | PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
||
343 | PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
||
344 | PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
345 | PIN_CR(GPIOB_GYRO_DRDY, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
||
346 | PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
||
347 | PIN_CR(GPIOB_ACCEL_INT_N, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX)) |
||
348 | #define VAL_GPIOBODR (PIN_ODR_LOW(GPIOB_PIN0) | \
|
||
349 | PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) | \ |
||
350 | PIN_ODR_LOW(GPIOB_POWER_EN) | \ |
||
351 | PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) | \ |
||
352 | PIN_ODR_LOW(GPIOB_PIN4) | \ |
||
353 | PIN_ODR_HIGH(GPIOB_COMPASS_DRDY) | \ |
||
354 | PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) | \ |
||
355 | PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) | \ |
||
356 | PIN_ODR_HIGH(GPIOB_COMPASS_SCL) | \ |
||
357 | PIN_ODR_HIGH(GPIOB_COMPASS_SDA) | \ |
||
358 | PIN_ODR_HIGH(GPIOB_IR_SCL) | \ |
||
359 | PIN_ODR_HIGH(GPIOB_IR_SDA) | \ |
||
360 | PIN_ODR_HIGH(GPIOB_IR_INT) | \ |
||
361 | PIN_ODR_HIGH(GPIOB_GYRO_DRDY) | \ |
||
362 | PIN_ODR_HIGH(GPIOB_SYS_UART_UP) | \ |
||
363 | PIN_ODR_HIGH(GPIOB_ACCEL_INT_N)) |
||
364 | |||
365 | /*
|
||
366 | * GPIOC setup:
|
||
367 | *
|
||
368 | * PC0 - DRIVE_SENSE1 (input analog)
|
||
369 | * PC1 - SYS_INT_N (output opendrain low 50MHz)
|
||
370 | * PC2 - PIN2 (input floating)
|
||
371 | * PC3 - PATH_DCSTAT (input floating)
|
||
372 | * PC4 - PIN4 (input floating)
|
||
373 | * PC5 - PATH_DCEN (output pushpull low 50MHz)
|
||
374 | * PC6 - DRIVE_ENC2B (input floating)
|
||
375 | * PC7 - DRIVE_ENC2A (input floating)
|
||
376 | * PC8 - SYS_PD_N (output opendrain high 50MHz)
|
||
377 | * PC9 - SYS_REG_EN (input floating)
|
||
378 | * PC10 - SYS_UART_RX (input floating)
|
||
379 | * PC11 - SYS_UART_TX (input floating)
|
||
380 | * PC12 - PIN12 (input pullup)
|
||
381 | * PC13 - ACCEL_SS_N (output pushpull high 50MHz)
|
||
382 | * PC14 - GYRO_SS_N (output pushpull high 50MHz)
|
||
383 | * PC15 - PIN15 (input floating)
|
||
384 | */
|
||
385 | 37bacabf | Thomas Schöpping | #define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_INT_N) | \
|
386 | PIN_IGNORE(GPIOC_SYS_PD_N)) & 0
|
||
387 | e545e620 | Thomas Schöpping | #define VAL_GPIOCCRL (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \
|
388 | 37bacabf | Thomas Schöpping | PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
389 | e545e620 | Thomas Schöpping | PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
390 | PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
391 | PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
392 | PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
||
393 | PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
394 | PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
395 | #define VAL_GPIOCCRH (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \
|
||
396 | PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
397 | PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
398 | PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
399 | PIN_CR(GPIOC_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
400 | PIN_CR(GPIOC_ACCEL_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
||
401 | PIN_CR(GPIOC_GYRO_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
||
402 | PIN_CR(GPIOC_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
403 | #define VAL_GPIOCODR (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) | \
|
||
404 | PIN_ODR_LOW(GPIOC_SYS_INT_N) | \ |
||
405 | PIN_ODR_LOW(GPIOC_PIN2) | \ |
||
406 | PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) | \ |
||
407 | PIN_ODR_LOW(GPIOC_PIN4) | \ |
||
408 | PIN_ODR_LOW(GPIOC_PATH_DCEN) | \ |
||
409 | PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) | \ |
||
410 | PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) | \ |
||
411 | PIN_ODR_HIGH(GPIOC_SYS_PD_N) | \ |
||
412 | PIN_ODR_HIGH(GPIOC_SYS_REG_EN) | \ |
||
413 | PIN_ODR_HIGH(GPIOC_SYS_UART_RX) | \ |
||
414 | PIN_ODR_HIGH(GPIOC_SYS_UART_TX) | \ |
||
415 | PIN_ODR_LOW(GPIOC_PIN12) | \ |
||
416 | PIN_ODR_HIGH(GPIOC_ACCEL_SS_N) | \ |
||
417 | PIN_ODR_HIGH(GPIOC_GYRO_SS_N) | \ |
||
418 | PIN_ODR_LOW(GPIOC_PIN15)) |
||
419 | |||
420 | /*
|
||
421 | * GPIOD setup:
|
||
422 | *
|
||
423 | * PD0 - OSC_IN (input floating)
|
||
424 | * PD1 - OSC_OUT (input floating)
|
||
425 | * PD2 - SYS_WARMRST_N (output opendrain high 50MHz)
|
||
426 | * PD3 - PIN3 (input floating)
|
||
427 | * PD4 - PIN4 (input floating)
|
||
428 | * PD5 - PIN5 (input floating)
|
||
429 | * PD6 - PIN6 (input floating)
|
||
430 | * PD7 - PIN7 (input floating)
|
||
431 | * PD8 - PIN8 (input floating)
|
||
432 | * PD9 - PIN9 (input floating)
|
||
433 | * PD10 - PIN10 (input floating)
|
||
434 | * PD11 - PIN11 (input floating)
|
||
435 | * PD12 - PIN12 (input floating)
|
||
436 | * PD13 - PIN13 (input floating)
|
||
437 | * PD14 - PIN14 (input floating)
|
||
438 | * PD15 - PIN15 (input floating)
|
||
439 | */
|
||
440 | 37bacabf | Thomas Schöpping | #define VAL_GPIODIGN 0 |
441 | e545e620 | Thomas Schöpping | #define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
442 | PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
443 | PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
||
444 | PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
445 | PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
446 | PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
447 | PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
448 | PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
449 | #define VAL_GPIODCRH (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
||
450 | PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
451 | PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
452 | PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
453 | PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
454 | PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
455 | PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
456 | PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
457 | #define VAL_GPIODODR (PIN_ODR_HIGH(GPIOD_OSC_IN) | \
|
||
458 | PIN_ODR_HIGH(GPIOD_OSC_OUT) | \ |
||
459 | PIN_ODR_HIGH(GPIOD_SYS_WARMRST_N) | \ |
||
460 | PIN_ODR_LOW(GPIOD_PIN3) | \ |
||
461 | PIN_ODR_LOW(GPIOD_PIN4) | \ |
||
462 | PIN_ODR_LOW(GPIOD_PIN5) | \ |
||
463 | PIN_ODR_LOW(GPIOD_PIN6) | \ |
||
464 | PIN_ODR_LOW(GPIOD_PIN7) | \ |
||
465 | PIN_ODR_LOW(GPIOD_PIN8) | \ |
||
466 | PIN_ODR_LOW(GPIOD_PIN9) | \ |
||
467 | PIN_ODR_LOW(GPIOD_PIN10) | \ |
||
468 | PIN_ODR_LOW(GPIOD_PIN11) | \ |
||
469 | PIN_ODR_LOW(GPIOD_PIN12) | \ |
||
470 | PIN_ODR_LOW(GPIOD_PIN13) | \ |
||
471 | PIN_ODR_LOW(GPIOD_PIN14) | \ |
||
472 | PIN_ODR_LOW(GPIOD_PIN15)) |
||
473 | |||
474 | /*
|
||
475 | * GPIOE setup:
|
||
476 | *
|
||
477 | * PE0 - PIN0 (input floating)
|
||
478 | * PE1 - PIN1 (input floating)
|
||
479 | * PE2 - PIN2 (input floating)
|
||
480 | * PE3 - PIN3 (input floating)
|
||
481 | * PE4 - PIN4 (input floating)
|
||
482 | * PE5 - PIN5 (input floating)
|
||
483 | * PE6 - PIN6 (input floating)
|
||
484 | * PE7 - PIN7 (input floating)
|
||
485 | * PE8 - PIN8 (input floating)
|
||
486 | * PE9 - PIN9 (input floating)
|
||
487 | * PE10 - PIN10 (input floating)
|
||
488 | * PE11 - PIN11 (input floating)
|
||
489 | * PE12 - PIN12 (input floating)
|
||
490 | * PE13 - PIN13 (input floating)
|
||
491 | * PE14 - PIN14 (input floating)
|
||
492 | * PE15 - PIN15 (input floating)
|
||
493 | */
|
||
494 | 37bacabf | Thomas Schöpping | #define VAL_GPIOEIGN 0 |
495 | e545e620 | Thomas Schöpping | #define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
496 | PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
497 | PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
498 | PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
499 | PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
500 | PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
501 | PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
502 | PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
503 | #define VAL_GPIOECRH (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
||
504 | PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
505 | PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
506 | PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
507 | PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
508 | PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
509 | PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
510 | PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
511 | #define VAL_GPIOEODR (PIN_ODR_LOW(GPIOE_PIN0) | \
|
||
512 | PIN_ODR_LOW(GPIOE_PIN1) | \ |
||
513 | PIN_ODR_LOW(GPIOE_PIN2) | \ |
||
514 | PIN_ODR_LOW(GPIOE_PIN3) | \ |
||
515 | PIN_ODR_LOW(GPIOE_PIN4) | \ |
||
516 | PIN_ODR_LOW(GPIOE_PIN5) | \ |
||
517 | PIN_ODR_LOW(GPIOE_PIN6) | \ |
||
518 | PIN_ODR_LOW(GPIOE_PIN7) | \ |
||
519 | PIN_ODR_LOW(GPIOE_PIN8) | \ |
||
520 | PIN_ODR_LOW(GPIOE_PIN9) | \ |
||
521 | PIN_ODR_LOW(GPIOE_PIN10) | \ |
||
522 | PIN_ODR_LOW(GPIOE_PIN11) | \ |
||
523 | PIN_ODR_LOW(GPIOE_PIN12) | \ |
||
524 | PIN_ODR_LOW(GPIOE_PIN13) | \ |
||
525 | PIN_ODR_LOW(GPIOE_PIN14) | \ |
||
526 | PIN_ODR_LOW(GPIOE_PIN15)) |
||
527 | |||
528 | /*
|
||
529 | * GPIOF setup:
|
||
530 | *
|
||
531 | * PF0 - PIN0 (input floating)
|
||
532 | * PF1 - PIN1 (input floating)
|
||
533 | * PF2 - PIN2 (input floating)
|
||
534 | * PF3 - PIN3 (input floating)
|
||
535 | * PF4 - PIN4 (input floating)
|
||
536 | * PF5 - PIN5 (input floating)
|
||
537 | * PF6 - PIN6 (input floating)
|
||
538 | * PF7 - PIN7 (input floating)
|
||
539 | * PF8 - PIN8 (input floating)
|
||
540 | * PF9 - PIN9 (input floating)
|
||
541 | * PF10 - PIN10 (input floating)
|
||
542 | * PF11 - PIN11 (input floating)
|
||
543 | * PF12 - PIN12 (input floating)
|
||
544 | * PF13 - PIN13 (input floating)
|
||
545 | * PF14 - PIN14 (input floating)
|
||
546 | * PF15 - PIN15 (input floating)
|
||
547 | */
|
||
548 | 37bacabf | Thomas Schöpping | #define VAL_GPIOFIGN 0 |
549 | e545e620 | Thomas Schöpping | #define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
550 | PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
551 | PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
552 | PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
553 | PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
554 | PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
555 | PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
556 | PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
557 | #define VAL_GPIOFCRH (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
||
558 | PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
559 | PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
560 | PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
561 | PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
562 | PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
563 | PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
564 | PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
565 | #define VAL_GPIOFODR (PIN_ODR_LOW(GPIOF_PIN0) | \
|
||
566 | PIN_ODR_LOW(GPIOF_PIN1) | \ |
||
567 | PIN_ODR_LOW(GPIOF_PIN2) | \ |
||
568 | PIN_ODR_LOW(GPIOF_PIN3) | \ |
||
569 | PIN_ODR_LOW(GPIOF_PIN4) | \ |
||
570 | PIN_ODR_LOW(GPIOF_PIN5) | \ |
||
571 | PIN_ODR_LOW(GPIOF_PIN6) | \ |
||
572 | PIN_ODR_LOW(GPIOF_PIN7) | \ |
||
573 | PIN_ODR_LOW(GPIOF_PIN8) | \ |
||
574 | PIN_ODR_LOW(GPIOF_PIN9) | \ |
||
575 | PIN_ODR_LOW(GPIOF_PIN10) | \ |
||
576 | PIN_ODR_LOW(GPIOF_PIN11) | \ |
||
577 | PIN_ODR_LOW(GPIOF_PIN12) | \ |
||
578 | PIN_ODR_LOW(GPIOF_PIN13) | \ |
||
579 | PIN_ODR_LOW(GPIOF_PIN14) | \ |
||
580 | PIN_ODR_LOW(GPIOF_PIN15)) |
||
581 | |||
582 | /*
|
||
583 | * GPIOG setup:
|
||
584 | *
|
||
585 | * PG0 - PIN0 (input floating)
|
||
586 | * PG1 - PIN1 (input floating)
|
||
587 | * PG2 - PIN2 (input floating)
|
||
588 | * PG3 - PIN3 (input floating)
|
||
589 | * PG4 - PIN4 (input floating)
|
||
590 | * PG5 - PIN5 (input floating)
|
||
591 | * PG6 - PIN6 (input floating)
|
||
592 | * PG7 - PIN7 (input floating)
|
||
593 | * PG8 - PIN8 (input floating)
|
||
594 | * PG9 - PIN9 (input floating)
|
||
595 | * PG10 - PIN10 (input floating)
|
||
596 | * PG11 - PIN11 (input floating)
|
||
597 | * PG12 - PIN12 (input floating)
|
||
598 | * PG13 - PIN13 (input floating)
|
||
599 | * PG14 - PIN14 (input floating)
|
||
600 | * PG15 - PIN15 (input floating)
|
||
601 | */
|
||
602 | 37bacabf | Thomas Schöpping | #define VAL_GPIOGIGN 0 |
603 | e545e620 | Thomas Schöpping | #define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
604 | PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
605 | PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
606 | PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
607 | PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
608 | PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
609 | PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
610 | PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
611 | #define VAL_GPIOGCRH (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
||
612 | PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
613 | PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
614 | PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
615 | PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
616 | PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
617 | PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
||
618 | PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
||
619 | #define VAL_GPIOGODR (PIN_ODR_LOW(GPIOG_PIN0) | \
|
||
620 | PIN_ODR_LOW(GPIOG_PIN1) | \ |
||
621 | PIN_ODR_LOW(GPIOG_PIN2) | \ |
||
622 | PIN_ODR_LOW(GPIOG_PIN3) | \ |
||
623 | PIN_ODR_LOW(GPIOG_PIN4) | \ |
||
624 | PIN_ODR_LOW(GPIOG_PIN5) | \ |
||
625 | PIN_ODR_LOW(GPIOG_PIN6) | \ |
||
626 | PIN_ODR_LOW(GPIOG_PIN7) | \ |
||
627 | PIN_ODR_LOW(GPIOG_PIN8) | \ |
||
628 | PIN_ODR_LOW(GPIOG_PIN9) | \ |
||
629 | PIN_ODR_LOW(GPIOG_PIN10) | \ |
||
630 | PIN_ODR_LOW(GPIOG_PIN11) | \ |
||
631 | PIN_ODR_LOW(GPIOG_PIN12) | \ |
||
632 | PIN_ODR_LOW(GPIOG_PIN13) | \ |
||
633 | PIN_ODR_LOW(GPIOG_PIN14) | \ |
||
634 | PIN_ODR_LOW(GPIOG_PIN15)) |
||
635 | |||
636 | #if !defined(_FROM_ASM_)
|
||
637 | #ifdef __cplusplus
|
||
638 | extern "C" { |
||
639 | #endif
|
||
640 | void boardInit(void); |
||
641 | #ifdef __cplusplus
|
||
642 | } |
||
643 | #endif
|
||
644 | #endif /* _FROM_ASM_ */ |
||
645 | |||
646 | #endif /* _BOARD_H_ */ |
||
647 | 53710ca3 | Marc Rothmann | |
648 | /** @} */ |