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1 58fe0e0b Thomas Schöpping
/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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 * STM32F4xx drivers configuration.
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 * The following settings override the default settings present in
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 * the various device driver implementation headers.
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 * Note that the settings for each driver only have effect if the whole
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 * driver is enabled in halconf.h.
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 *
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 * IRQ priorities:
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 * 15...0       Lowest...Highest.
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 *
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 * DMA priorities:
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 * 0...3        Lowest...Highest.
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 */
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#define STM32F4xx_MCUCONF
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/*
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 * Some old revisions of F4x MCU randomly chrashes with certain compiler options enabled.
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 * This flag makes the kernel dynamically detect the MCUs ID code and CPU ID and react accordingly.
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 * (see ChibiOS kernel: os/hal/ports/STM32/STM32F4xx/hal_lld.c)
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 */
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#define STM32_USE_REVISION_A_FIX
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/*
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 * HAL driver system settings.
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 */
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#define STM32_NO_INIT                       FALSE
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#define STM32_HSI_ENABLED                   TRUE
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#define STM32_LSI_ENABLED                   TRUE
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#define STM32_HSE_ENABLED                   TRUE
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#define STM32_LSE_ENABLED                   FALSE
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#define STM32_CLOCK48_REQUIRED              TRUE
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#define STM32_SW                            STM32_SW_PLL
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#define STM32_PLLSRC                        STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE                    8
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#define STM32_PLLN_VALUE                    336
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#define STM32_PLLP_VALUE                    2
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#define STM32_PLLQ_VALUE                    7
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#define STM32_HPRE                          STM32_HPRE_DIV1
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#define STM32_PPRE1                         STM32_PPRE1_DIV4
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#define STM32_PPRE2                         STM32_PPRE2_DIV2
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#define STM32_RTCSEL                        STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE                  8
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#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE                 192
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#define STM32_PLLI2SR_VALUE                 5
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#define STM32_PVD_ENABLE                    FALSE
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#define STM32_PLS                           STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE                 FALSE
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/*
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 * IRQ system settings.
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 */
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#define STM32_IRQ_EXTI0_PRIORITY            6
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#define STM32_IRQ_EXTI1_PRIORITY            6
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#define STM32_IRQ_EXTI2_PRIORITY            6
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#define STM32_IRQ_EXTI3_PRIORITY            6
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#define STM32_IRQ_EXTI4_PRIORITY            6
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#define STM32_IRQ_EXTI5_9_PRIORITY          6
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#define STM32_IRQ_EXTI10_15_PRIORITY        6
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#define STM32_IRQ_EXTI16_PRIORITY           6
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#define STM32_IRQ_EXTI17_PRIORITY           15
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#define STM32_IRQ_EXTI18_PRIORITY           6
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#define STM32_IRQ_EXTI19_PRIORITY           6
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#define STM32_IRQ_EXTI20_PRIORITY           6
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#define STM32_IRQ_EXTI21_PRIORITY           15
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#define STM32_IRQ_EXTI22_PRIORITY           15
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/*
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 * ADC driver system settings.
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 */
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#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1                  TRUE
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#define STM32_ADC_USE_ADC2                  FALSE
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#define STM32_ADC_USE_ADC3                  FALSE
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#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY         2
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#define STM32_ADC_ADC2_DMA_PRIORITY         2
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#define STM32_ADC_ADC3_DMA_PRIORITY         2
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#define STM32_ADC_IRQ_PRIORITY              6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
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/*
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 * CAN driver system settings.
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 */
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#define STM32_CAN_USE_CAN1                  TRUE
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#define STM32_CAN_USE_CAN2                  FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY         11
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#define STM32_CAN_CAN2_IRQ_PRIORITY         11
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/*
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 * DAC driver system settings.
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 */
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#define STM32_DAC_DUAL_MODE                 FALSE
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#define STM32_DAC_USE_DAC1_CH1              FALSE
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#define STM32_DAC_USE_DAC1_CH2              FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)
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/*
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 * GPT driver system settings.
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 */
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#define STM32_GPT_USE_TIM1                  FALSE
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#define STM32_GPT_USE_TIM2                  FALSE
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#define STM32_GPT_USE_TIM3                  FALSE
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#define STM32_GPT_USE_TIM4                  FALSE
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#define STM32_GPT_USE_TIM5                  FALSE
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#define STM32_GPT_USE_TIM6                  FALSE
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#define STM32_GPT_USE_TIM7                  FALSE
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#define STM32_GPT_USE_TIM8                  FALSE
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#define STM32_GPT_USE_TIM9                  FALSE
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#define STM32_GPT_USE_TIM11                 FALSE
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#define STM32_GPT_USE_TIM12                 FALSE
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#define STM32_GPT_USE_TIM14                 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY         7
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#define STM32_GPT_TIM2_IRQ_PRIORITY         7
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#define STM32_GPT_TIM3_IRQ_PRIORITY         7
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#define STM32_GPT_TIM4_IRQ_PRIORITY         7
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#define STM32_GPT_TIM5_IRQ_PRIORITY         7
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#define STM32_GPT_TIM6_IRQ_PRIORITY         7
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#define STM32_GPT_TIM7_IRQ_PRIORITY         7
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#define STM32_GPT_TIM8_IRQ_PRIORITY         7
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#define STM32_GPT_TIM9_IRQ_PRIORITY         7
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#define STM32_GPT_TIM11_IRQ_PRIORITY        7
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#define STM32_GPT_TIM12_IRQ_PRIORITY        7
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#define STM32_GPT_TIM14_IRQ_PRIORITY        7
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/*
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 * I2C driver system settings.
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 */
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#define STM32_I2C_USE_I2C1                  TRUE
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#define STM32_I2C_USE_I2C2                  TRUE
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#define STM32_I2C_USE_I2C3                  FALSE
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#define STM32_I2C_BUSY_TIMEOUT              50
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#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C1_IRQ_PRIORITY         5
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#define STM32_I2C_I2C2_IRQ_PRIORITY         5
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#define STM32_I2C_I2C3_IRQ_PRIORITY         5
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#define STM32_I2C_I2C1_DMA_PRIORITY         3
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#define STM32_I2C_I2C2_DMA_PRIORITY         3
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#define STM32_I2C_I2C3_DMA_PRIORITY         3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
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/*
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 * I2S driver system settings.
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 */
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#define STM32_I2S_USE_SPI2                  FALSE
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#define STM32_I2S_USE_SPI3                  FALSE
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#define STM32_I2S_SPI2_IRQ_PRIORITY         10
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#define STM32_I2S_SPI3_IRQ_PRIORITY         10
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#define STM32_I2S_SPI2_DMA_PRIORITY         1
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#define STM32_I2S_SPI3_DMA_PRIORITY         1
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#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
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/*
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 * ICU driver system settings.
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 */
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#define STM32_ICU_USE_TIM1                  FALSE
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#define STM32_ICU_USE_TIM2                  FALSE
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#define STM32_ICU_USE_TIM3                  FALSE
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#define STM32_ICU_USE_TIM4                  FALSE
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#define STM32_ICU_USE_TIM5                  FALSE
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#define STM32_ICU_USE_TIM8                  FALSE
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#define STM32_ICU_USE_TIM9                  FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY         7
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#define STM32_ICU_TIM2_IRQ_PRIORITY         7
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#define STM32_ICU_TIM3_IRQ_PRIORITY         7
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#define STM32_ICU_TIM4_IRQ_PRIORITY         7
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#define STM32_ICU_TIM5_IRQ_PRIORITY         7
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#define STM32_ICU_TIM8_IRQ_PRIORITY         7
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#define STM32_ICU_TIM9_IRQ_PRIORITY         7
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/*
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 * MAC driver system settings.
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 */
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#define STM32_MAC_TRANSMIT_BUFFERS          2
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#define STM32_MAC_RECEIVE_BUFFERS           4
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#define STM32_MAC_BUFFERS_SIZE              1522
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#define STM32_MAC_PHY_TIMEOUT               100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY         13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
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/*
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 * PWM driver system settings.
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 */
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#define STM32_PWM_USE_ADVANCED              FALSE
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#define STM32_PWM_USE_TIM1                  FALSE
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#define STM32_PWM_USE_TIM2                  FALSE
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#define STM32_PWM_USE_TIM3                  TRUE
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#define STM32_PWM_USE_TIM4                  FALSE
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#define STM32_PWM_USE_TIM5                  FALSE
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#define STM32_PWM_USE_TIM8                  FALSE
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#define STM32_PWM_USE_TIM9                  FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY         7
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#define STM32_PWM_TIM2_IRQ_PRIORITY         7
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#define STM32_PWM_TIM3_IRQ_PRIORITY         7
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#define STM32_PWM_TIM4_IRQ_PRIORITY         7
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#define STM32_PWM_TIM5_IRQ_PRIORITY         7
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#define STM32_PWM_TIM8_IRQ_PRIORITY         7
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#define STM32_PWM_TIM9_IRQ_PRIORITY         7
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/*
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 * SDC driver system settings.
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 */
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#define STM32_SDC_SDIO_DMA_PRIORITY         3
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#define STM32_SDC_SDIO_IRQ_PRIORITY         9
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#define STM32_SDC_WRITE_TIMEOUT_MS          1000
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#define STM32_SDC_READ_TIMEOUT_MS           1000
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#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
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#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
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#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
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/*
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 * SERIAL driver system settings.
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 */
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#define STM32_SERIAL_USE_USART1             TRUE
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#define STM32_SERIAL_USE_USART2             FALSE
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#define STM32_SERIAL_USE_USART3             FALSE
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#define STM32_SERIAL_USE_UART4              FALSE
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#define STM32_SERIAL_USE_UART5              FALSE
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#define STM32_SERIAL_USE_USART6             FALSE
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#define STM32_SERIAL_USART1_PRIORITY        12
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#define STM32_SERIAL_USART2_PRIORITY        12
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#define STM32_SERIAL_USART3_PRIORITY        12
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#define STM32_SERIAL_UART4_PRIORITY         12
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#define STM32_SERIAL_UART5_PRIORITY         12
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#define STM32_SERIAL_USART6_PRIORITY        12
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/*
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 * SPI driver system settings.
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 */
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#define STM32_SPI_USE_SPI1                  TRUE
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#define STM32_SPI_USE_SPI2                  FALSE
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#define STM32_SPI_USE_SPI3                  FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI1_DMA_PRIORITY         1
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#define STM32_SPI_SPI2_DMA_PRIORITY         1
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#define STM32_SPI_SPI3_DMA_PRIORITY         1
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#define STM32_SPI_SPI1_IRQ_PRIORITY         10
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#define STM32_SPI_SPI2_IRQ_PRIORITY         10
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#define STM32_SPI_SPI3_IRQ_PRIORITY         10
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#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
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/*
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 * ST driver system settings.
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 */
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#define STM32_ST_IRQ_PRIORITY               8
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#define STM32_ST_USE_TIMER                  2
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/*
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 * UART driver system settings.
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 */
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#define STM32_UART_USE_USART1               FALSE
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#define STM32_UART_USE_USART2               TRUE
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#define STM32_UART_USE_USART3               TRUE
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#define STM32_UART_USE_UART4                FALSE
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#define STM32_UART_USE_UART5                FALSE
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#define STM32_UART_USE_USART6               FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY      12
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#define STM32_UART_USART2_IRQ_PRIORITY      12
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#define STM32_UART_USART3_IRQ_PRIORITY      12
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#define STM32_UART_UART4_IRQ_PRIORITY       12
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#define STM32_UART_UART5_IRQ_PRIORITY       12
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#define STM32_UART_USART6_IRQ_PRIORITY      12
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#define STM32_UART_USART1_DMA_PRIORITY      0
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#define STM32_UART_USART2_DMA_PRIORITY      0
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#define STM32_UART_USART3_DMA_PRIORITY      0
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#define STM32_UART_UART4_DMA_PRIORITY       0
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#define STM32_UART_UART5_DMA_PRIORITY       0
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#define STM32_UART_USART6_DMA_PRIORITY      0
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#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
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/*
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 * USB driver system settings.
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 */
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#define STM32_USB_USE_OTG1                  FALSE
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#define STM32_USB_USE_OTG2                  FALSE
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#define STM32_USB_OTG1_IRQ_PRIORITY         14
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#define STM32_USB_OTG2_IRQ_PRIORITY         14
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#define STM32_USB_OTG1_RX_FIFO_SIZE         512
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#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
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#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
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#define STM32_USB_OTG_THREAD_STACK_SIZE     128
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#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
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/*
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 * WDG driver system settings.
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 */
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#define STM32_WDG_USE_IWDG                  FALSE
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#endif /* MCUCONF_H */