amiro-os / include / amiro / radio / a2500r24a.hpp @ a47d64ad
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1 | 58fe0e0b | Thomas Schöpping | #ifndef A2500R24A_HPP_
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2 | #define A2500R24A_HPP_
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3 | |||
4 | #include <ch.hpp> |
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5 | |||
6 | namespace amiro {
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7 | |||
8 | class HWSPIDriver; |
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9 | |||
10 | class A2500R24A : public chibios_rt::BaseStaticThread<256> { |
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11 | |||
12 | public:
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13 | |||
14 | struct A2500R24AConfig {
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15 | }; |
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16 | |||
17 | /**
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18 | * Return types of getCheck()
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19 | */
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20 | enum {
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21 | CHECK_OK = 0x00u,
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22 | CHECK_FAIL = 0x01u,
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23 | }; |
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24 | |||
25 | //private:
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26 | |||
27 | struct registers {
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28 | uint8_t IOCFG2; |
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29 | uint8_t IOCFG1; |
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30 | uint8_t IOCFG0; |
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31 | uint8_t FIFOTHR; |
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32 | uint8_t SYNC1; |
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33 | uint8_t SYNC0; |
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34 | uint8_t PKTLEN; |
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35 | uint8_t PKTCTRL1; |
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36 | uint8_t PKTCTRL0; |
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37 | uint8_t ADDR; |
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38 | uint8_t CHANNR; |
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39 | uint8_t FSCTRL1; |
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40 | uint8_t FSCTRL0; |
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41 | uint8_t FREQ2; |
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42 | uint8_t FREQ1; |
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43 | uint8_t FREQ0; |
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44 | uint8_t MDMCFG4; |
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45 | uint8_t MDMCFG3; |
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46 | uint8_t MDMCFG2; |
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47 | uint8_t MDMCFG1; |
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48 | uint8_t MDMCFG0; |
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49 | uint8_t DEVIATN; |
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50 | uint8_t MCSM2; |
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51 | uint8_t MCSM1; |
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52 | uint8_t MCSM0; |
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53 | uint8_t FOCCFG; |
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54 | uint8_t BSCFG; |
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55 | uint8_t AGCCTRL2; |
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56 | uint8_t AGCCTRL1; |
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57 | uint8_t AGCCTRL0; |
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58 | uint8_t WOREVT1; |
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59 | uint8_t WOREVT0; |
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60 | uint8_t WORCTRL; |
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61 | uint8_t FREND1; |
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62 | uint8_t FREND0; |
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63 | uint8_t FSCAL3; |
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64 | uint8_t FSCAL2; |
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65 | uint8_t FSCAL1; |
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66 | uint8_t FSCAL0; |
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67 | uint8_t RCCTRL1; |
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68 | uint8_t RCCTRL0; |
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69 | uint8_t FSTEST; |
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70 | uint8_t PTEST; |
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71 | uint8_t AGCTEST; |
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72 | uint8_t TEST2; |
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73 | uint8_t TEST1; |
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74 | uint8_t TEST0; |
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75 | uint8_t reserved_0x2F; |
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76 | }__attribute__((packed)); |
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77 | |||
78 | struct registerStrobe {
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79 | uint8_t configurationRegister[offsetof(A2500R24A::registers, reserved_0x2F)+1];
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80 | uint8_t SRES; |
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81 | uint8_t SFSTXON; |
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82 | uint8_t SXOFF; |
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83 | uint8_t SCAL; |
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84 | uint8_t SRX; |
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85 | uint8_t STX; |
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86 | uint8_t SIDLE; |
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87 | uint8_t reserved_0x37; |
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88 | uint8_t SWOR; |
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89 | uint8_t SPWD; |
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90 | uint8_t SFRX; |
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91 | uint8_t SFTX; |
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92 | uint8_t SWORRST; |
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93 | uint8_t SNOP; |
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94 | uint8_t PATABLE; |
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95 | uint8_t RX_TX_FIFO; |
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96 | }__attribute__((packed)); |
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97 | |||
98 | struct registerStatus {
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99 | uint8_t configurationRegister[offsetof(A2500R24A::registers, reserved_0x2F)+1];
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100 | uint8_t PARTNUM; |
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101 | uint8_t VERSION; |
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102 | uint8_t FREQEST; |
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103 | uint8_t LQI; |
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104 | uint8_t RSSI; |
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105 | uint8_t MARCSTATE; |
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106 | uint8_t WORTIME1; |
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107 | uint8_t WORTIME0; |
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108 | uint8_t PKTSTATUS; |
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109 | uint8_t VCO_VC_DAC; |
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110 | uint8_t TXBYTES; |
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111 | uint8_t RXBYTES; |
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112 | uint8_t RCCTRL1_STATUS; |
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113 | uint8_t RCCTRL0_STATUS; |
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114 | }__attribute__((packed)); |
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115 | |||
116 | enum {
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117 | A2500R24A_PARTNUM = 0x80u,
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118 | A2500R24A_VERSION = 0x03u,
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119 | }; |
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120 | |||
121 | enum {
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122 | // For register access below address 0x30 the burst mode is available
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123 | // to read multiple bytes
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124 | SPI_BURST_ENA = 0x40u,
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125 | SPI_BURST_DIS = 0x00u,
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126 | // For addresses above (and including) 0x30 either the status or strobe access
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127 | // has to be choosen, instead of burst mode
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128 | SPI_STATUS_ACCESS = 0x40u,
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129 | SPI_STROBE_ACCESS = 0x00u,
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130 | // Read or write the register address
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131 | SPI_READ = 0x80u,
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132 | SPI_WRITE = 0x00u,
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133 | }; |
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134 | |||
135 | public:
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136 | A2500R24A(HWSPIDriver* driver); |
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137 | virtual ~A2500R24A();
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138 | |||
139 | chibios_rt::EvtSource* getEventSource(); |
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140 | msg_t configure(A2500R24AConfig* config); |
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141 | |||
142 | /**
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143 | * Check the presence of the radio chip by reading
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144 | * the identifier register and comparing it to the standard
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145 | * value
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146 | */
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147 | uint8_t getCheck(); |
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148 | |||
149 | protected:
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150 | virtual msg_t main();
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151 | |||
152 | private:
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153 | inline void updateSensorData(); |
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154 | |||
155 | private:
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156 | |||
157 | HWSPIDriver* driver; |
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158 | chibios_rt::EvtSource eventSource; |
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159 | |||
160 | }; |
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161 | |||
162 | } /* amiro */
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163 | |||
164 | #endif /* A2500R24A_HPP_ */ |